MATEC Web Conf.
Volume 201, 20182017 The 3rd International Conference on Inventions (ICI 2017)
|Number of page(s)||3|
|Section||Invention of electrical engineering system|
|Published online||14 September 2018|
120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process
Department of Computer Science and Information Engineering, Asia University, 500, Lioufeng Rd., Taichung 41354, Taiwan.
2 Department of Medical Research, China Medical University Hospital, China Medical University, Taichung, Taiwan.
* Corresponding author: email@example.com
In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.
© The Authors, published by EDP Sciences, 2018
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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