MATEC Web of Conferences
Volume 44, 20162016 International Conference on Electronic, Information and Computer Engineering
|Number of page(s)||4|
|Section||Electronics, Information and Engineering Application|
|Published online||08 March 2016|
Gate Engineering in SOI LDMOS for Device Reliability
Department of Computer Science and Information Engineering, Asia University,, 500, Lioufeng Rd., Taichung 41354, Taiwan
2 School of Software and Microelectronics, Peking University, Beijing, China
a Corresponding author: email@example.com
A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF) SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source) where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..
© Owned by the authors, published by EDP Sciences, 2016
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