MATEC Web Conf.
Volume 201, 20182017 The 3rd International Conference on Inventions (ICI 2017)
|Number of page(s)||3|
|Section||Invention of numerical scheme and application|
|Published online||14 September 2018|
Analysis of Anti-JFET for 600V VDMOS and HCI Reliability
Department of Computer Science and Information Engineering, Asia University, 500, Lioufeng Rd., Taichung 41354, Taiwan.
2 School of Software and Microelectronics, Peking University, Beijing, China.
3 Department of Medical Research, China Medical University Hospital, China Medical University, Taichung, Taiwan.
* Corresponding author: firstname.lastname@example.org
In VDMOS device the anti-JFET concentration has important role for determining the breakdown voltage and on-resistance of the device. Because higher N-drift doping concentration can provide the very best on-resistance of the device but also decrease breakdown voltage. It also has a proportional relationship with threshold voltage degradation. In this paper, we report the anti-JFET implantation energy influence effect electric potential distribution, the highest impact ionization shifted from the silicon surface to deeper. It will have less hot carrier impact, and we have found higher breakdown voltage. The anti-JEFT implantation is critical for on-resistance off-state breakdown voltage optimization, However the high field and high impact ionization near the gate region will cause severe hot carrier Injection problem. The general expectation of high voltage VDMOS transistor is to have higher breakdown voltage, less degradation due to hot carrier injection and better on-resistance.
© The Authors, published by EDP Sciences, 2018
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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