MATEC Web Conf.
Volume 201, 20182017 The 3rd International Conference on Inventions (ICI 2017)
|Number of page(s)||3|
|Section||Invention of electrical engineering system|
|Published online||14 September 2018|
Study of HCI Reliability for PLDMOS
Department of Computer Science and Information Engineering, Asia University, 500, Lioufeng Rd., Taichung 41354, Taiwan.
2 School of Software and Microelectronics, Peking University, Beijing, China.
3 Department of Medical Research, China Medical University Hospital, China Medical University, Taichung, Taiwan.
* Corresponding author: firstname.lastname@example.org
In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.
© The Authors, published by EDP Sciences, 2018
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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