MATEC Web Conf.
Volume 108, 20172017 International Conference on Mechanical, Aeronautical and Automotive Engineering (ICMAA 2017)
|Number of page(s)||4|
|Section||Modern Electronic Information Technology|
|Published online||31 May 2017|
The Influence of Gate Scaling to Electrical Characteristics on n-MOS FinFET
Department of Electronics Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang
This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation. Start from 20 nm device, then scaling to 22 nm 28 nm and 32 nm. Therefrom Minimos-NT function has used for biasing to giving two electrical characteristics as the drain current saturation and the threshold voltage. From these consequences can offer the subthreshold swing and the drain-induced barrier lowering by calculation. The results found that threshold voltage inversely proportional to saturated drain current, the subthreshold swing and the drain-induced barrier lowering. The short channel effect has affected to 20 nm model by highest DIBL. Therefore should be adjust the gate length and the oxide thickness properly to improve this effect.
© The Authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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