The Influence of Gate Scaling to Electrical Characteristics on nMOS FinFET

This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation. Start from 20 nm device, then scaling to 22 nm 28 nm and 32 nm. Therefrom Minimos-NT function has used for biasing to giving two electrical characteristics as the drain current saturation and the threshold voltage. From these consequences can offer the subthreshold swing and the drain-induced barrier lowering by calculation. The results found that threshold voltage inversely proportional to saturated drain current, the subthreshold swing and the drain-induced barrier lowering. The short channel effect has affected to 20 nm model by highest DIBL. Therefore should be adjust the gate length and the oxide thickness properly to improve this effect.


Introduction
The introduced of Tri-gate transistor technology by Intel corporation in 2 nd quarterly of 2011.Intel brought the new technology to giving good performance for them devices.3-D transistor as known as FinFET.This is a choice to make new computer architecture.In 2011 M. Zakir Hossain and his researcher team shown electrical characteristics of SOI tri-gate FinFET.The result of this paper explain about basic characteristics such as the current and voltage characteristics (I-V), the threshold voltage, the electron mobility and field mobility [1].In 2012 they proposed about the drain-induced barrier lowering (DIBL) and short channel effect (SCE).Influence of DIBL and SCE is coming together.DIBL make a drain to gate electron barrier lower.In a same way I-V and threshold voltage will strange from theory, and downward a subthreshold characteristics.It make device cannot change to cut-off stage at low voltage [2].This concept make author interested in effects from scaling a device to solve problems for improved a structure of FinFET prototype and fabrication in the future.

Saturation Drain Current (I ds,Sat )
While the drain current has no longer affected by the drain voltage, and where the FinFET acts more like a current source, has called the current saturation.This current value can be solve by [3]: W g , gate width (nm) L g , gate length (nm) C ox , Gate Oxide capacitance (F/nm)

Threshold Voltage (V th )
The minimum gate-to-source voltage differential that was needs to create a conducting path between the source and drain.This is the most significant characteristic that provide the value of power that used to switch the FinFET from off stage to on stage and show the switching performance of devices.The threshold voltage can giving from [4]: n i, Electron and Hole Concentration without Doping (cm -3 ) t si , Silicon Thickness (nm) h, Channel Height (nm) w si , Silicon width (nm) η, Carrier Concentration (cm -3 ).

Subthreshold Swing (SS)
The subthreshold swing is logarithm of drain current relationship of drain current and gate voltage that The reduction of threshold voltage at higher drain voltages by the lowering of potential barrier on drain that affect to gate and Solve by [6] Low th th Low

Experimental
This paper separated to two experiments part consist of the FinFET structure and the relationship between the electrical characteristics with the gate length.The first part, create a device structure on GTS framework [7] from 20 nm gate length and then increase L g to 22 nm, 28 nm, and 32 nm 10 nm silicon layer width and 25 nm silicon thickness with 1 nm gate oxide thickness on the top of 70 nm p-type substrate with buried oxide (BOX). In

Characteristics with gate length relationship
The electrical characteristics of devices is the important point to determine a performance.From second part of experiment obtain the drain current saturation, the threshold voltage for calculate the subthreshold swing and the drain induced barrier lowering, to comparebetween characteristics and enlargement of gate length.An enlargement of gate length determined a saturation current in Figure 3.The deportment of I ds was lowering with increase of L g .Due to adding of electron concentration in channel that affect to them mobility.This effect bring I ds downward about 0.1 μA per increasing of L g .It was giving I ds on 20 nm ate length at 18.10 µA, 22 nm at 17.90 µA, 28 nm at 16.50 µA and 32 nm at 15.80 µA.Therefore I ds (Sat) behaviour on device with 20 nm L g is better.In Figure 4, the threshold voltage has increased with L g but after biased I ds / V gs giving amiss result of 20 nm.It was coming with a little SCE because in this experiment vary only L g .The threshold voltage of 20 nm gate length about 0.625 volt, 22nm at 0.636 volt, 28 nm at 0.643 and 32 nm gate length has 0.662 volt thus SCE affect to this characteristics directly while gate length was increased.Normally, V th will increasing with L g since the gate length has increased and require more energy to turn device stage to turn-on.The subthreshold swing is important attribute to obtain DIBL with gate length that shown in Figure 6.Influence of DIBL was directly to SS from lowering of barrier between channels and drain junction that affect to threshold voltage.DIBL on 20 nm gate length was about 23 mV/V, 22 nm at 13.30 mV/V, 28nm at 12.80 mV/V and 32 nm L g approximate about 12.30 mV/V.The DIBL giving to known a problem from SCE.If it was high, this device will be out of characteristics.1, Increasing of gate length will bring the threshold voltage up but the drain current, the subthreshold swing and DIBL are inversely proportional.The highest DIBL of 20 nm giving a least V th that affected by short channel effect not from decreasing of gate length.

Summary
Investigate into FinFET structure simulation is best way to understand operating of device.Many of problems has found from this experiment.In this article provides experiments to bring up effects from designed device structure, which are two effects as the short channel effect and the drain-induced barrier lowering.From the result found relationship between the drain current saturation, the threshold voltage, the subthreshold swing and the drain-induced barrier lowering.Increasing of gate length directly with V th but reverse with I ds,sat , SS and

Figure 1 . 2 . 4
Figure 1.Relationship between the drain current and the gatesource voltage

Figure 4 .
Figure 4. Threshold voltage with gate length

Figure 5 .
Figure 5. Subthreshold Swing with gate lengthIn Figure5shown the subthreshold swing has decreased by the gate length increasing, as more drain current passing in shorter L g .From logarithm square root of drain current and gate-source voltage provide the SS

Table 1 .
Electrical characteristics of FinFET

I ds(sat) (μA) V th (V) (V dd = 1 V) SS (mV/dec) DIBL (mV/V)
The short channel effect has found in 20nm model therefore an adjustment of gate length will reach electrical characteristics suitability.