MATEC Web of Conferences
Volume 57, 20164th International Conference on Advancements in Engineering & Technology (ICAET-2016)
|Number of page(s)||4|
|Section||Electronic & Electrical Engineering|
|Published online||11 May 2016|
- Kazuteru Namba, Takashi Katagiri, Hideo Ito, “Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop” Journal of Electronic Testing, Vol. 29, pp 545-554, 2013. [CrossRef]
- Massoud Pedram, “A New Design for Double Edge-Triggered Flip-flops” International Journal of Electronics Communication and Computer Engineering Volume 4, pp 412-417, 2013.
- Stojanovic, V.; Oklobdzija, V.G., “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” Solid-State Circuits, IEEE Journal of, vol. 34, pp.536-548, 1999. [CrossRef]
- Nedovic, Nikola; Aleksic, M.; Oklobdzija, V.G., “Conditional pre-charge techniques for powerefficient dual-edge clocking,” Low Power Electronics and Design. Proceedings of the 2002 International Symposium, vol. 3, pp.56-59, 2002.
- S. Wimer and I. Koren, “The Optimal fan-out of clock network for power minimization by adaptive gating,” IEEE Trans. VLSI Syst., vol. 20, pp. 1772–1780, 2012. [CrossRef]
- Yasmeen Khan,” Power Optimization of Linear Feedback Shift Register Using Clock Gating ,” Volume 7, PP. 109-115, 2013.
- S. Wimer and I. Koren, “The Optimal fan-out of clock network for power minimization by adaptive gating”, IEEE Trans. VLSI Syst., vol. 20, pp. 1772–1780, 2012. [CrossRef]
- M. Muller, S. Simon, H. Gryska, A. Wortmann, and S. Buch, “Low power synthesizable register files for processor and IP cores”, The VLSI J., vol. 39, pp. 131–155, 2006. [CrossRef]
- A. G. M. Strollo and D. De Caro, “Low power flip-flop with clock gating on master and slave latches”, Electron. Lett., vol. 36, pp. 294–295, 2000. [CrossRef]
- J. Kathuria, M. Ayoub, M. Khan, and A. Noor, “A review of Clock Gating Techniques”, MIT Int. J. Electron. and Commun. Engin., vol. 1, pp. 106–114, 2011.
- Dr. Neelam R. Prakash, Akash, “Clock Gating for Dynamic Power Reduction in Synchronous Circuits”, International Journal of Engineering Trends and Technology (IJETT), vol. 4, pp. 513-519, 2013.
- P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A test vector inhibiting technique for low energy BIST design,” in Proc. 17th IEEE VLSI Test Symp.,vol 3, pp. 407–412, 1999. [CrossRef]
- S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, “Low power BIST by filtering non-detecting vectors,” J. Electron. Test.-Theory Appl., vol. 16, pp. 193–202, 2000. [CrossRef]
- F. Corno, M. Rebaudengo, M. Reorda, and M. Violante, “A new BIST architecture for low power circuits,” in Proc. Eur. Test Workshop, vol 5, pp. 160–164, 1999.
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