A P-N SEQUENCE GENERATOR USING LFSR WITH DUAL EDGE TRIGGER TECHNIQUE

This paper represents the design and implementation of a low power 4-bit LFSR using Dual edge triggered flip flop. A linear feedback shift register (LFSR) is assembled by N number of flip flops connected in series and a combinational logic generally xor gate. An LFSR can generate random number sequence which acts as cipher in cryptography. A known text encrypted over long PN sequence, in order to improve security sequence made longer ie 128 bit; require long chain of flip flop leads to more power consumption. In this paper a novel circuit of random sequence generator using dual edge triggered flip flop has been proposed. Data has been generated on every edge of flip flop instead of single edge. A DETFF-LFSR can generate random number require with less number of clock cycle, it minimizes the number of flip flop result in power saving. In this paper we concentrates on the designing of power competent Test Pattern Generator (TPG) using four dual edge triggered flip-flops as the basic building block, overall there is reduction of power around 25% by using these techniques.


INTRODUCTION
Random numbers is essential to cryptography, cryptographic protocol AES, RSA, DES etc is depends on random number for encryption.Data security demands the generated number must be random and non deterministic known as pseudo random number.Pseudo number generator built from Linear Feedback Shift Register (LFSR) with judicious selection of the XOR taps feedback path.Pseudo random number generators generate a stream of numbers in a known pattern.The pattern is typically very long and it is hard to recognize the sequence of numbers is ordered.For example 128 bit LFSR requires to implement 32 PRNG with 96 bit are hidden protection comes from hidden number.Both hardware and software implementations of LFSRs are common.LFSR can be implemented in the hardware and it makes useful in applications that may require fast generation of a pseudo random sequence [12] LFSR is preferred for test pattern generator and error correction due to its simple hardware structure.TPG is a device which generates uniqueness of patterns to test the Circuit under Test (CUT) shown in fig1.In computing, a linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state.The most commonly used linear function of single bits is XOR.Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value.The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state.Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle.However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.

LINEAR-FEEDBACK SHIFT REGISTER
LFSR is a linear feedback shift register whose input bit is a linear function of previous function that contains the signal through the register from one bit to the next mostsignificant when it is clocked.Figure 3 shows the block diagram of LFSR, a 4-bit LFSR generate 24-1 different non zero bit pattern by performing exclusive-OR gate on the outputs of two or more of the flip-flops and feeding those outputs back in to the input of one of the flip-flops.
An L bit LFSR generates the maximal length up to 2^L-1 combinations, figure4.

LFSR WITH DET-FF
In this section a design of proposed FLSR has been discussed.
(i) High-level latch: A high level latch provides result on high level of clock.In fig5, on high level of clk Q=D.[9].ither is low level.This DETFF require a combinerelement (mux) which combine the data accessed on high and low level of latch.Select line of multlplexer route the latch output to output trminal.MUX will select according to the clock provided as the select line.In detects the data on both of the levels and hence provides the same data at the output which is provided at the input of both latches Area of DETFF is about a half of that of edge-triggered FFs.[11] By combining all these blocks we perform the dual edge triggering and we got the same output which is provided at the input D. there will be total 16 patterns generated, but to initiate the LFSR we cannot feed the pattern of "0000" because the shift register would be stuck at this pattern because as we know that if we provide 0 at the input of the XOR gate than the output of XOR gate will be 0 always.So we have to provide any other pattern except all 0's.The LFSR is initiated by the input 0110, and it provides the output patterns as shown in figure 10 and 11. Figure 11 shows the output waveform of the LFSR.Cdence virtuoso circuit compser used for schematic design and Cadence spectre simulator using to obtained simulation result on cmos 90nm technology.
As the enable pin gets high the LFSR gets initialized.The first pattern is generated around 1.2 ns and about near to 3.2 ns all of the desired patterns has been generated, after this the pattern starts repeating.We analyzed that total time taken for the generation of the patterns is approximately 2ns.

Figure 1 .
Figure 1.Random number generator 2 DETFF In digital system clock signal has its special role; input clock signal controls the working rhythm of the chip.The clock signal controls flip-flops to sample and store their input data on active edge.To improve data rate clock frequency must increases, but in recent design performance of the flip-flop improved by increasing the active edge; in stead of accessing data on single edge accesson both edge.Dual edge triggered flip-flop (DETFF) can access data on both edges of the clock; it

Figure 5 .Figure 6 .
Figure 5. High-Level Latch (ii) Low-Level Latch: A high level latch provides result on low level of clock.In fig6, on low level of clk Q=D.

Figure 7 .
Figure 7. 2:1 MUX (iv) Dual Edge triggered flip flop: A Dual edge triggered flip flop has two latch , one os high level sensetive andither is low level.This DETFF require a combinerelement (mux) which combine the data accessed on high and low level of latch.Select line of multlplexer route the latch output to output trminal.MUX will select according to the clock provided as the select line.In detects the data on both of the levels and hence provides the same data at the output which is provided at the input of both latches Area of DETFF is about a half of that of edge-triggered FFs.[11]By combining all these blocks we perform the dual edge triggering and we got the same output which is provided at the input D.