Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging

School of Engineering and Science, Curtin University Sarawak Campus, CDT 250, 98009 Miri, Sarawak, Malaysia

Abstract

The flip chip bonding technology is widely used in electronic packaging as a result of improvements towards mechanical performance of layered structures. However, thermal mismatch shear and peeling stress are often induced by the differences of the material properties and geometries of bond layer during the high temperature change at operating stage. Intrinsically, these thermo-mechanical stresses play a very significant role in the design and reliability of the flip chip package. Therefore, this project aims to develop a methodology to find optimized bonding material thermo-mechanical properties and geometries in relation to the packaging layers in order to eliminate or reduce thermal mismatch stresses that occur in multi-layered structures in electronic packaging. The closed-form solution of thermo-mechanical analysis of bi-material assembly with bond layer is provided. Parametric study will be carried out in order to study the influence of bond layer parameters on interfacial thermal stresses of a flip chip assembly. These parameters include Young modulus, Coefficient of Thermal Expansion (CTE), Poisson’s ratio and thickness of the bond layer. It is found that the shearing stresses and peeling stresses decreased considerably at the interface with the increase of bond layer Young Modulus and thickness. On the other side, bond layer CTE and Poisson ratio show almost no significant effect on the interfacial shearing stress and peeling stress along the interface in a bi-material assembly.