Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO₂/TiSi₂ 18 nm PMOS

¹ Centre of Micro and Nano Engineering (CeMNE) Universiti Tenaga Nasional (UNITEN), 43000 Kajang, Selangor, Malaysia
² Institute of Microengineering and Nanoelectronics (IMEN) Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia

^* Corresponding author: norani@uniten.edu.my

Abstract

Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO₂ was used as the gate dielectric ad TiO₂ was used as the gate material. The transistor HfO₂/TiSi₂ 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method’s practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source–drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO₂/TiSi₂ 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi’s signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was -0.291339.