MATEC Web of Conferences
Volume 65, 20162016 The International Conference on Nanomaterial, Semiconductor and Composite Materials (ICNSCM 2016)
|Number of page(s)||5|
|Section||Intelligent Materials and Intelligent Systems|
|Published online||06 July 2016|
- Weiwei Shan Member IEEE “Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware”, IEEE Transaction on instrumentation and measurement, Vol. 62 No. 10 (2013).
- Akkar.M.L and Giraud. C (2001), “An implementation of DES and AES secure against some attacks”, in Proc. Cryptographic Hardware Embedded Syst, Paris, France, pp. 309–318.
- Weiwei Shan, Xin Chen, Bo Li, Peng Cao, Jie Li, Gugang Gao, and Longxing Shi (2013), “Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware”, IEEE Transactions on Instrumentation and Measurement, Vol. 62, No.10, pp. 2716–2724. [CrossRef]
- William Stallings (2005), “Cryptography and Network Security Principles and Practices”, Prentice Hall, November 16, pp. 24–28, 56–83.
- Himanshu Thapliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad-500019, India.
- Shamim Akhter, “VHDL Implementation of Fast NXN Multiplier Based on Vedic Mathematics”, Jaypee Institute of Information Technology, University, Noida, 201307 UP, INDIA, 2007 IEEE.
- Behrouz AForouzan, DebdeepMukhopadhyay, “Cryptography and Network Security”, second edition, Tata McGraw Hill Education Pvt Ltd, 2008.
- NitishAggarwal, KartikAsooja, Saurabh ShekharVerma, SapnaNegi, “ An Improvement in the Restoring Division Algorithm”, IEEE 2009.
- Sumit Vaidya, Deepak Dandekar, “Delay-Power Performance Comparison of multipliers in VLSI circuit design”, International Journal of Computer Networks & Communications (IJCNC) , Vol. 2, No. 4, July 2010.
- J. Wu, Y. Shi, and M. Choi, “Measurement and evaluation of power analysis attacks on asynchronous S-box,” IEEE Trans. Instrum.Meas. vol. 61, no. 10, pp. 2765–2775, 2012. [CrossRef]
- J. Li, Y. Lv, H. Sun, and W. Shan, “A power analysis resistant DES cryptographic algorithm and its hardware design,” in Proc. 3rd Int. Conf. Digit. Manuf. Autom., GuiLin, China, pp. 121–124, 2012.
- ChiranthE, ChakravarthyH.V.A, NagamohanareddyP, UmeshT.H, Chethan KumarM, “Implementation of RSA Cryptosystem Using Verilog”, International Journal of Scientific & Engineering Research Volume 2, Issue 5, May–2011
- Bhaskar Ganapathi Hegde, P.R. Vaya, “Anefficient hardware model for RSA Encryption system usingVedic mathematics”, International Conference on Communication Technology and System Design 2011.
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