Improved Mask Protected DES using RSA Algorithm

: The data encryption standard is a pioneering and farsighted standard which helped to set a new paradigm for encryption standards. But now DES is considered to be insecure for some application. Asymmetric mask protected DES is an advanced encryption method for effectively protecting the advanced DES. There are still probabilities to improve its security. This paper propose a method, which introduce a RSA key generation scheme in mask protected DES instead of plain key, which result in enhancement in the security of present asymmetric mask protected DES. We further propose a Vedic mathematical method of RSA implementation which reduce the complexity of computation in RSA block thereby resulting in reduced delay (four times)that improves the performance of overall system. The software implementation was performed using Xilinx 13.2 and Model-Sim was used for the simulation environment.


I Introduction
Cryptography is usually referred to, as the study of securing information.The aim of cryptography is not to hide the existence of a message but it rather hides its meaning.Encryption is the process of converting plain text to cipher text.The process of converting cipher text back to plain text is called decryption [4], [7].There are two basic cryptographic techniques one in symmetric or private key cryptography and another is asymmetric key cryptography .Data Encryption Standard (DES) is a widely-used method of data encryption using a private (secret) key that was judged so difficult to break [9].Most symmetric encryption schemes today are based on this structure.Although this is considered "strong" encryption, DES is one of the symmetric encryption algorithm, which is considered to be insecure now a days.Asymmetric mask protected DES is also a symmetric cryptography where an extra masking technique is used to increase the security of DES shown in fig 1 and fig 2. There are still probabilities to improve its security and efficiency.Here, a new method is introduced where in the already existing key generation scheme is replaced by RSA encryption.RSA prime factorization involved in it increases the security thus making it resistant to side channel attack such as correlation power analysis attacks and differential power analysis attack [2], [3]which is used to crack the plain text [10], [11].Further Vedic mathematical calculations are involved to reduce the complexity of encryption in RSA block which further improves the efficiency of the proposed method [13].The rest of the paper is organized as follows.Section II describes the asymmetric mask protected DES, and Vedic Implementation.Section III describes the proposed improved encryption mechanism using RSA algorithm.Section IV describes the simulation environment and results.Section V contains conclusion and the future scope.

II. BACKGROUND a. Asymmetric Mask Protected DES
The asymmetric mask protected DES is a data encryption standard where a masking technique is introduced in the normal DES algorithm [1].Like most of the encryption schemes mask protected DES expects two inputs -the plain text to be encrypted and the secret key.The main idea in this method is to add different random numbers in the first, last and internal rounds.This method also has 16 rounds of operation similar to DES.Hence multiple mask operations added at different moments and locations helps to break the relation between power consumption and key thereby improving security.

b. Vedic Implementation
The RSA Algorithm is the most popular asymmetric key cryptographic algorithm..The RSA Algorithm is based on the mathematical functions that are easy to find and multiply the large numbers together, but it is extremely difficult to factor their product [5].The public and private keys in RSA are based on very large numbers.To increase the computation speed with minimized hardware the Vedic mathematics [6]multiplication principle is used.These architectures are used to improve the speed of the RSA algorithm with reduced hardware [7], [8].On other hand, one has to accept the fact that securing always increases the complexity of an encryption procedure thereby consuming more power for encryption and decryption.Secondly this complexity reduces the speed of data processing thereby increasing the delay.Hence security as always compromised with speed and throughput performance to some extent in any encryption techniques.In the proposed method the existence of array multiplier is replaced by Vedic multiplier in the RSA block.This replacement produced four times reduced delay values when compared to the usual array multiplier used in RSA.To increase the computation speed, the multiplication principle of Vedic mathematics is used.And also "URDHVA-TIRYAKBHYAM" is the sutra (principle) which is used to compute the multiplication.The significance of this technique is that it computes the partial products in one step and avoids shifting operation which reduces the complexity of the algorithm and saves both the execution time and hardware.This ultimately improves the speed of RSA algorithm [13], [12].Hence the secure dual protection of asymmetric mask protected DES and RSA is achieved with less complexity.

IV. Result and discussion
The proposed method is simulated using ModelSim 6.3 g and code in written in verilog using Xilinx.Fig. 5 shows the encrypted output of proposed method.The input and output details are given below.Even if the attack sample is increased five times, the attacker still cannot gain the key when improved asymmetric masked DES using RSA is used.Hence the proposed method is resistant to differential power analysis attack and correlation power analysis attack.

V. CONCLUSION
The improvedmask protected DES encryption mechanism using RSA algorithm is a full featured circuit including key generation, data encryption and data decryption.Each sub component and top module of the proposed encryption mechanism was implemented using verilog and was simulated using ModelSim which proved to be functionally correct.Dual security is achieved by the use of random numbers and RSA algorithm thus resistant to side channel attack.The complexity in the proposed system is reduced by using Vedic mathematical calculation which produced four times lesser delay values.Since the demand for higher levels of security is increasing the use of the proposed mechanism makes the entire algorithm difficult to crack.As a result, security is enhanced.The obtained Less delay values promotes high speed and low power consumption, thus promoting efficient hardware implementation on FPGAs.Future work can be carried out on cadence.The proposed method can also be implemented in Bluetooth technology and hybrid encryption.The work can also be extended to large bits such as 256 or 1024 or even longer and can be used in many applications where security is of major concern.

Fig. 5
Fig.5 Encrypted output waveform for proposed system

Fig. 6
Fig.6 Decrypted waveform for proposed system