MATEC Web of Conferences
Volume 22, 2015International Conference on Engineering Technology and Application (ICETA 2015)
|Number of page(s)||6|
|Section||Electric and Electronic Engineering|
|Published online||09 July 2015|
- Cui, L. H. 2011. Design of a high precision bandgap voltage reference. International Conference on Electronic and Mechanical Engineering and Information Technology, pp: 2187–2190.
- Raman, M.S., Kifle T., Bhattacharya E. and Bhat, K.N. 2006. Physical model for the resistivity and temperature coefficient of resistivity in heavily doped polysilicon. IEEE Transaction on Electron Devices, 53(8): 1885–1892. [CrossRef]
- Uang C-M, Chuang H-M, Tsai S-F, Thei K-B, Lai P-H, Fu S-I, Tsai Y-Y and Liu W-C. 2004. Temperature-dependent characteristics of diffused and polysilicon resistor for ULSI application. The Fourth International Workshop on Junction Technology, pp: 293–296.
- Virkus, R., Weiser, D., Green, K., Richardson, D. and Westphal, G. 2001. Modeling of non-linear polysilicon resistors for analog circuit design. International Conference on Microelectronic Test Structures, pp: 89–91.
- Ko, S.Y., Kim, J.S., Lim, G.H., and Kim, S.K. 2006. A new poly silicon resistor model considering geometry dependent voltage characteristics for the deep sub-micron process. International Conference on Micro-electronic Test Structures, pp: 27–30.
- Ren, Z., Li, X., Hu, S.J., Chen, S.M, Zhao, Y.H. and Shi, Y.L. 2012. A correlation-considered variation-aware interconnect parasitic profile extraction method. IEEE Transaction on Electron Devices, 59(9): 2321–2326. [CrossRef]
- Stine, B.E., Boning, D.S., Chung, J.E., Camilletti, L., Kruppa, F., Equi, E.R, Loh, W., Prasad, S., Muthukrishnan, M., Towery D., Berman M. and Kapoor A. 1998. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. IEEE Transaction on Electron Devices, 45(3): 665–679. [CrossRef]
- Yeh, C.T., Chen, C.F., Hung Y.T., Su C.T., Yang T., Chen K.C. and Lu C.Y. 2011. A novel tow-step poly CMP to improve dishing and erosion effect on self-aligned floating gate process. International Symposium on Semiconductor Manufacturing and e-Manufacturing and Design Collaboration Symposium, pp: 1–10.
- Zhou, Y., Li, Z., Tian, Y.X., Shi, W.P. and Liu. F. 2007. A new methodology for interconnect parasitics extraction considering photo-lithography effects. Asia and South Pacific Design Automation Conference, pp: 450–455.
- Sun, L-J, Cheng, J, Ren, Z. , Shang G-B, Hu, S-J, Chen, S-M, Zhao, Y-H and Shi, Y-L. 2014. Extraction of geometry-related interconnect variation based on parasitic capacitance data. IEEE Electron Device Letters, 35(10): 980–982. [CrossRef]
- Holland, A.S., Reeves, G.K., Bhaskaran, M. and Sriram S. 2009. Analytical and finite-element modeling of a cross kelvin resistor test structure for low specific contact resistivity. IEEE Transaction on Electron Devices, 56(10): 2250–2254. [CrossRef]
- Chang Y-W, Chang H-W, Hsieh C-H, Lai H-C, Lu T-C, Ting W.C., Ku, J. and Lu C-Y. 2004. A novel simple CBCM method free from charge injection-induced errors. IEEE Electron Device Letters, (25) 5: 262–264. [CrossRef]
- Synopsys Inc. 2013. Raphael Interconnect Analysis Program Reference Manual, Version H-2013.03.
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.