MATEC Web of Conferences
Volume 22, 2015International Conference on Engineering Technology and Application (ICETA 2015)
|Number of page(s)||6|
|Section||Electric and Electronic Engineering|
|Published online||09 July 2015|
Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation
1 School of Information Science and Technology, East China Normal University, Shanghai, China
2 Shanghai IC R&D Center, Shanghai, China
3 Huali Microelectronics Corporation, Shanghai, China
In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.
Key words: poly-silicon resistor / temperature-dependent voltage characteristics (TDVC) / parasitic capacitance / SPICE model
© Owned by the authors, published by EDP Sciences, 2015
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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