Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

In this paper, the SPICE model of poly resistor is accurately developed based on silicon data. To describe the non-linear R-V trend, the new correlation in temperature and voltage is found in non-silicide poly-silicon resistor. A scalable model is developed on the temperature-dependent characteristics (TDC) and the temperature-dependent voltage characteristics (TDVC) from the R-V data. Besides, the parasitic capacitance between poly and substrate are extracted from real silicon structure in replacing conventional simulation data. The capacitance data are tested through using on-wafer charge-induced-injection error-free charge-based capacitance measurement (CIEF-CBCM) technique which is driven by non-overlapping clock generation circuit. All modeling test structures are designed and fabricated through using 40nm CMOS technology process. The new SPICE model of poly-silicon resistor is more accurate to silicon for analog circuit simulation.


INTRODUCTION
Poly-silicon resistor is widely used as an important device in CMOS analog circuit design [1] such as band-gap, integrator or DAC. It is necessary to use an accurate model for circuit simulation in DC and AC performance.
In the conventional way of industry, the modeling equations which include temperature-dependent characteristics (TDC) [2][3] and voltage-dependent characteristics (VDC) [4][5] are same in silicide and non-silicide poly-silicon resistor. With the CMOS technology being developed into 40nm, VDC has a secondary temperature effect only on non-silicide poly-silicon resistor. Hence, the old SPICE model equations can't meet the real silicon data. On the other hand, the accurate parasitic capacitance of poly-silicon resistor is also a key [6] in SPICE model. However, they are always traditionally simulated by field-solver. Due to some process variation such as etching [7], erosion [8] and optical proximity correction (OPC) [9], the field-solver simulation data loses accuracy without real silicon verification.
In this paper, the SPICE models of poly-silicon resistor in 40 nm technology have been optimized based on silicon data. In the section 2 and section 3, the temperature-dependent voltage characteristics (TDVC) are found to replace VDC and a novel scalable model is established with TDC and TDVC in non-silicide poly-silicon resistor. In the section 2 and section 4, the capacitance test structure is designed to extract real parasitic data using an efficient and precise on-wafer test technique from the group former work [10].

MODELING TEST STRUCTURE DESIGN
The topological modeling structure of three-terminal poly-silicon resistor in this paper is shown in Figure 1. R main is main part resistance of poly-silicon, and C 1 and C 2 is a couple of symmetrical capacitance between poly and substrate. According to Figure 1, test structures are designed and measured to describe these components in a precise way. Figure 2 shows the layout of I-V test structures of both N + and P + non-silicide poly-silicon resistor corresponding to different width (W) from 0.36μm to 3.6μm and Length (L) from 4.5μm to 72.9μm. The numbers of sheet resistance is defined as L/W.

I-V test structure
All I-V structures are designed with four terminals and they are tested by Kelvin technique [11] using Agilent B1500A under -40 , 25 and 125 . The calculation of resistance is shown in Equation 1, the step of force current is set up by 16μA and the sense voltage is limited under the range of -4V to 4V:  (1)

Parasitic capacitance test technique and structure
From the group former work [10], the on-wafer capacitance test technique has been proved to be an efficient and precise way. The schematic is shown in Figure 3.
The charge-induced error-free charge-based capacitance measurement (CIEF CBCM) [12] in the dashed frame is driven by non-overlapping clock generation circuit to simplify the test procedure. The Figure 4 shows the pulse program. In step 1, V IN1 is input with a traditional pulse and V IN2 is set up to ground. In step 2, both V IN1 and V IN2 share the same pulse with step1. As a result, the system parasitic capacitance C par is de-embedded. I step1 and I step2 are recorded on the pad of V dd by two steps. Then C load can be calculated in Equation 2, where f is the frequency of pulse and V dd is the working voltage. Agilent 8110A is used to generate pulse and Agilent B1500a is used to measure the average current: Several numbers of the poly finger are designed in parallel to compose C load between poly and substrate. The layout of C load is designed in Figure 5 and NF is defined as the number of Finger. To avoid apparent non-linear effects of I-V, silicide poly-silicon resistor is chosen because of its metal-like performance and the same geometry structure with non-silicide poly-silicon resistor. In Figure 5, L is fixed in 15μm, W changes from 0.36μm to 1.8μm. The whole layout of on-wafer test technique with poly structure is shown in Figure 6. The layout occupies only 40μm μm area. All Kelvin R-V test structures and CBCM capacitance test structure with C load are fabricated through using 40nm LP CMOS technology. And then in the next two sections, all silicon data are from on-wafer measurement on Cascade probe station.

R-V MODELING FLOW
Based on Equation 1, R-V data is transferred from I-V data. Figure 7 shows the R-V data of P + non-silicide poly-silicon resistor V.S. old model simulation. When the poly sizes get smaller, the R-V curves under different temperature show the larger difference in curvature. VDC is influenced by temperature more and more serious in sub-nano CMOS process. The old model format which is same as the metal-performance-like silicide poly-silicon resistor can't meet the new global effect TDVC in Figure 7. A new scalable modeling flow based on silicon data is set up as shown in the following steps.

3.1
Step 1: R 0 modeling R 0 is defined as the 0V resistance under 25 The formula of R 0 is shown in Equation 3, where rsh is sheet resistivity, dl and dw is the correction between real size and design size in on side: (3) Figure 8 shows the fitting result of R 0 modeling of all geometry size, where the dots are silicon data and the solid lines are model simulation.  (5) to W tw r tc 1 (6) too W tww r tc 2

Step 2: TDC modeling
The fitting result of TDC modeling in four nominal geometry sizes is shown in Figure 9.

Step 3: TDVC modeling
To describe the TDVC on silicon data, Voltage-dependent coefficient vcoeff in Equation 8 and Equation 9 not only considers the scale influence of W and N, but also should include temperature factor DTEMP. With the poly size getting smaller in Figure  5, TDVC becomes more and more serious, so TDVC modeling parameter tvcr is scalable with W to describe this global effect in Equation 10. In TDVC modeling process, vco, vcw, vcn, tvw and tvo are fitting parameters: (9) tvo W tvw tvcr (10) The fitting result of TDVC modeling in P + /N + non-silicide poly-silicon resistor is shown in Figure 10. All silicon data and simulation are normalized by R T0 to make the fitting result clearly. The simulation result from new model considered with TDVC is much better than old model. In Table 1, all obtained fitting parameters in the whole modeling flow are summarized by P + and N + non-slicide poly-silicon resistor.

Conventional method of extraction
The poly-silicon resistor structure is shown in Figure  11 with its parasitic capacitance to the substrate in one-side. The vertical overlap capacitance (C ov ) between the bottom of poly to the substrate, the fringing capacitance between the L-direction (C fL ) and W-direction (C fW ) sidewall of poly to the substrate are all considered to be extracted. In the conventional way in the industry, the parasitic capacitance of poly-silicon resistor is simulated by field solver such as Synopsys Raphael without any silicon verification. However, such parasitic capacitance is deeply influenced by the geometry variation [10] in the sub-nano CMOS technology. In Figure 12, only simplified poly structure can be accepted in Raphael [13] without any variation considering, so the parasitic capacitance can't be accurate to the silicon.

On-silicon way of extraction
Based on the analysis of Figure 1 and Figure 11, the method of parasitic capacitance extraction is built in Equation 11. To extract the parasitic capacitance in a scalable way in Equation 12 and 13, C ov are normalized to W L in C ov0 , C fw and C fl are normalized to W and L in C f0 .  Figure 13 shows silicon data extraction V.S. conventional Raphael simulation, and all capacitance is normalized by NF and L. From Figure 13, silicon data is smaller than simulation data about 5%~9%, the error can be considered as cause of geometry variation due to process. According to Equation 11,Equation 12 and Equation 13, C ov0 and C f0 are extracted in Table 2. All N + /P + silicide and non-silicide poly-silicon resistors can share these equations and parameters in their SPICE model because they are in the same geometry structure.     In this paper, a complete on-silicon modeling flow has been developed. Figure 14 has summarized the whole flow from test design to measurement and modeling. A new SPICE model with novel TDVC and silicon-based parasitic capacitance is updated for 40nm CMOS technology analog circuit simulation design. Compared with conventional model in R-V and parasitic capacitance, the new one is much nearer to silicon and can fit data better.