MATEC Web Conf.
Volume 232, 20182018 2nd International Conference on Electronic Information Technology and Computer Engineering (EITCE 2018)
|Number of page(s)||7|
|Section||3D Images Reconstruction and Virtual System|
|Published online||19 November 2018|
Improved Simulated Annealing Genetic Algorithm based Low power mapping for 3D NoC
Hefei University of Technology, 230009 HeFei, China
2 School of Computer Science and Information Engineering, Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, 230009 HeFei, China
Mapping of IP(Intellectual Property) cores onto NoC(Network-on-Chip) architectures is a key step in NoCbased designs. Energy is the key parameter to measure the designs. Therefore, we propose an Improved Simulated Annealing Genetic Alogrithm, abbreviated as ISAGA. The algorithm combines the parallelism of Genetic Algorithm(GA) and the local search ability of Simulated Annealing(SA). We improve the initial population selection of GA to get the lower power consumption mapping scheme. The experimental results show that compared with the GA, ISAGA has good convergence and can search the optimal solution quickly, which can effectively reduce the power consumption of the system. In the case of 124 IP cores, the average power consumption of the ISAGA is reduced by 32.0% compared with the GA.
© The Authors, published by EDP Sciences, 2018
This is an open access article distributed under the terms of the Creative Commons Attribution License 4.0 (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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