Study of HCI Reliability for PLDMOS

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and


Introduction
Most of the studies about hot-carrier effects concentrated on n-MOSFETs rather than p-MOSFETs simply because the hot-carrier induced problems are more serious in n-MOSFETs due to longer mean free path, hence higher energy of electrons. For example, peak substrate current in n-MOSFETs is about 3 to 4 orders larger than in P-MOSFETs. In near-micrometre CMOS integrated circuits, N-MOSFETs are known to fail earlier than P-MOSFETs.
However, the empirical relationship between P-MOSFET DC lifetime and lifetime monitor is usually obtained over narrow V, ranges, for example V, near the peak of ISuB or IG, and may not be suitable for lifetime modeling for arbitrary stressing waveforms. A general expression which can well describe device degradation over a wide range of bias is thus required. In the following, hot-carrier-induced degradation and gate current model in SC p-MOSFETs are presented. The lifetime of a SC p-MOSFET is found to correlate with I, over a wide range of V. Using this correlation and a gate current model based on the lucky electron approach, the lifetime of a SC p-MOSFET under pulse stress can be estimated [4].
However, the use of power semiconductor devices is exponentially growing, because increased efficiency is required in energy conversion process and better circuit solution is continuously proposed. One of the strongest motivations for research in this field is the largest market segment of automotive body control power. In some cases, P-channel power devices can be a better option than the n-channel devices, when the lower performance of the PLDMOS (i.e. Lower switching speed and higher RON) can be less important than the possibility of significant circuit simplification. The new rising market of LED driver for automotive interior and exterior lights, LED daytime running lights and LED front lights is a typical example. One of the key devices in this product is the PLDMOS, which is, for example used in the lowdropout (LDO) regulator of the converter. A low-dropout or LDO regulator is a DC linear voltage regulator, which can operate with a very small input-output differential voltage. The substitution of the bipolar device with the PLDMOS transistor leads to several advantages such as a lower minimum operating voltage, higher efficiency operation and lower heat dissipation. In this case, the use of the n-channel lateral DMOS transistor would need some more circuitry and cannot be used in open loop conditions [2].

Experimental setup
The experimental setup was designed as flowchart in Fig.1 (b). Practically, the comparisons of the device degradation are performed by confrontment of the IV curve before and after stress time on the device structures. Thus, degradation trend for drain current saturation (IDsat) were calculated for different stress time until we will get 2% of IDsat degradation. Before that we have measured Vgmax from Ig-Vg curve at -40V of drain voltage and -5V of gate voltage. According to that we were selected V gmax and the stress voltage -40V of V DD . After stress, the drain current saturation calculated at 40V of drain and selected gate voltage (Vgmax from Ig-Vg curve).
Degradation, thermodynamic HCI and classical lucky electron models were invoked in the device simulation to perform the interface trap generation due to HCI. A process of electrons tunnel through a barrier in the presence of a high electric field was taken into account by using Fowler-Nordheim model. While, the luckyelectron model provides an estimate of the probability that some carriers in silicon will be transmitted to the oxide by overcoming the local energy barrier at the Si-SiO 2 interface [5][6][7].

Gate current model
Since, gate current is a better monitor than substrate current for device degradation in p-MOSFET's modelling of gate current is important. Unlike n-MOSFET's, p-MOSFET's exhibit the largest gate current when biased in the saturation region at low V. The gate current has a long mean free path. Also, the Si-SiO2 barrier height is lower for electrons and the vertical field at low VG favours electron injection [4].

Results and discussion
Simulations As we are shown in Fig 2, we have measured Vgmax from different devices and we have plotted Ig-Vg curves from different devices. The Vgmax was measured at V DD =-40V and Vg=-5V. We have found lower Igmax for device4 as shown in Fig 2. This Igmax was better than other devices. From this Igmax curve, we have measured Vgmax. So, as we know HCI degradations is because of trapped charges into the oxide region of Si/SiO 2 interface and HCI degradation will be more with more traps that occurs in oxide regions. We perform HCI stress test for them until that device reaches 2% of IDsat the degradation and measured drain saturation current shift (∆IDsat)at V DD =-40V and selected gate voltage from gate current curve and we summarize all HCI results with different condition device performances. When we analyse the results, we can explain that the lower gate current device has very good HCI performance. We have proved our device lifetime, improved according to the gate current measurements. The comparison life time curves between device Life Time(Years) Curve Between Stress Time (Sec) and ID/ID (%) shown in Fig 3. It is possible for us to achieve this HCI performance because we put lots of effort to redesign the device so that impact-ionization hotspot should happen at a location away from the gate and below the surface so that the hot carriers that generate and experience high lateral applied field should not reach or overcome the Si/Sio2 potential barrier and become trapped into gate-oxide region. So we kept this in mind and re-designed our device which helps to get better HCI performance and device can pass HCI life time reliability test.
The increasing rate of ΔID/ID with stress-time becomes small after extended stress. Extrapolating the short-term stress data to obtain device lifetimes can introduce large errors. To avoid this, we stress the devices long enough so that, ΔID/ID exceeds or nearly reaches the lifetime criteria. τ is defined as the time at which ΔID/ID reaches a certain percentage (2-4%). The devices were stressed with fixed VD, and varying VG. In both cases, the correlation can be expressed as τ α IG -m with m = 2.25 as shown in

Conclusion
Some of the hot carriers generated in the bird's beak area are injected into the gate oxide and the others constitute the substrate current. The majority of hot carriers injected into the gate oxide is collected by the gate electrode and constitute the gate current. Both of the gate current and substrate current are a good monitor to predict device degradation. While gate current is a direct measurement of the injected carriers into the gate oxide, it is very sensitive to the trapping mechanism (during TCAD simulation) and is very low. In our present work, we measured gate current and it makes easier to measure. Although high-voltage LDMOSFETs have a large depletion area in the drift region (large part of the generation current by impact ionization in this region constitutes a gate current), gate current is an indirect way of measuring the hot carrier injection.