MATEC Web Conf.
Volume 125, 201721st International Conference on Circuits, Systems, Communications and Computers (CSCC 2017)
|Number of page(s)||6|
|Published online||04 October 2017|
- S. Alam, U. Varetto, GROMACS on Hybrid CPU-GPU and CPU-MIC Clusters: Preliminary Porting Experiences, Results and Next Steps, At: http://www.praceri.eu/IMG/pdf/wp120.pdf [Google Scholar]
- K. Asanovic, et al., The landscape of parallel computing research: A view from Berkeley (2006) http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.pdf [Google Scholar]
- Cǎlin Bîra, Programming environment for parallel accelerators, PhD Thesis, UPB, ETTI, Department of Electronic Devices, Circuits and Architectures (2013) http://arh.pub.ro/papers/LucrareDoctorat_v9d.pdf [Google Scholar]
- L. Jianguo, Running GROMACS on GPUs: a Benchmark Study (2014) At: https://www.acrc.a-star.edu.sg/docs/ASTAR [Google Scholar]
- S. C. Kleene, “General Recursive Functions of Natural Numbers”, in Math. Ann., 112, (1936) [Google Scholar]
- E. Lindahl, Molecular Simulation with GROMACS on CUDA GPUs (2013) At: http://on-demand.gputechconf.com/gtc/2013/webinar/gromacs-kepler-gpus-gtc-express-webinar.pdf [Google Scholar]
- M. Malita, G. Ştefan, D. Thiébaut, “Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation” ACM SIGARCH Computer Architecture News, Volume 35, Issue 5, pp. 32–38 (2007) [CrossRef] [Google Scholar]
- D. Mihǎiţǎ, N-Body Problem. Application, on a Map-Reduce Accelerator, to Molecular Dynamics, Master Thesis, Politehnica University of Bucharest, (2016) [Google Scholar]
- M. Plotnikov, GROMACS for Intel Xeon PhiTM Coprocessor At: https://software.intel.com/en-us/articles/gromacs-for-intel-xeon-phi-coprocesso [Google Scholar]
- D. E. Shaw, et al., “Anton, A Special-Purpose Machine for Molecular Dynamics Simulation”. Communications of the ACM. 51 (7): 91–97 (2008) [CrossRef] [Google Scholar]
- G. Ştefan, et al., “The CA1024: A Fully Programmable System-On-Chip for Cost-Effective HDTV Media Processing”, in Hot Chips: A Symposium on High Performance Chips, Memorial Auditorium, Stanford University (2006) At: https://youtu.be/HMLT4EpKBAw 35:00 [Google Scholar]
- G. Ştefan, “One-chip TeraArchitecture”, Proceedings of the 8th Applications and Principles of Information Science Conference. Okinawa (2009) http://arh.pub.ro/gstefan/teraArchitecture.pdf [Google Scholar]
- G. Ştefan, M. Maliţa, “Can One-Chip Parallel Computing Be Liberated From Ad Hoc Solutions? A Computation Model Based Approach and Its Implementation”, 18th Inter. Conf. on Ciruits, Systems, Communications and Computers, Santorini, 582–597 (2014) [Google Scholar]
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.