Open Access
MATEC Web of Conferences
Volume 54, 2016
2016 7th International Conference on Mechanical, Industrial, and Manufacturing Technologies (MIMT 2016)
Article Number 12005
Number of page(s) 5
Section Electronic application technology
Published online 22 April 2016
  1. K. H. Cheng, C. W. Su, & K. F. Chang. A high linearity, fast-locking pulsewidth control loop with digitally programmable duty cycle correction for wide range operation. Solid-State Circuits, IEEE Journal of, 43(2), 399–413. (2008). [CrossRef] [Google Scholar]
  2. F. Mu, & C. Svensson. Pulsewidth control loop in high-speed CMOS clock buffers. Solid-State Circuits, IEEE Journal of, 35 (2), 134–141. (2000) [CrossRef] [Google Scholar]
  3. H. Y. Huang, W. M. Chiu, & W. M. Lin. Pulsewidth control loop circuit using combined charge pumps and miller scheme. In Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on (Vol. 2, pp. 1539–1542). IEEE. (2004, October) [CrossRef] [Google Scholar]
  4. Y. M. Wang, & J. S. Wang. An all-digital 50% duty-cycle corrector. In Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International Symposium on (Vol. 2, pp. II-925). IEEE. (2004) [Google Scholar]
  5. Y. M. Wang, C. F. Hu, Y. J. Chen, & J. S. Wang. An all-digital pulsewidth control loop. In Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (pp. 1258–1261). IEEE. (2005, May) [Google Scholar]
  6. J. Gu, J. Wu, D. Gu, M. Zhang, & L. Shi. All-digital wide range precharge logic 50% duty cycle corrector. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 20 (4), 760–764. (2012) [CrossRef] [Google Scholar]
  7. J. R. Su, T. W. Liao & C. C. Hung. Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle. In Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian> (pp. 305–308). IEEE. (2012, November) [Google Scholar]
  8. C. C. Chung & C. J. Li. A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. In VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on (pp. 1–4). IEEE. (2013, April) [Google Scholar]
  9. C. C. Chung, D. Sheng, & S. E. Shen. High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 22(5), 1096–1105. (2014) [CrossRef] [Google Scholar]
  10. J. C. Ha, J. H. Lim, Y. J. Kim, W. Y. Jung & J. K. Wee. Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface.Electronics Letters, 44 (22), 1300–1301. (2008) [CrossRef] [Google Scholar]

Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.

Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.

Initial download of the metrics may take a while.