MATEC Web of Conferences
Volume 40, 20162015 International Conference on Mechanical Engineering and Electrical Systems (ICMES 2015)
|Number of page(s)||4|
|Section||Power electronics engineering|
|Published online||29 January 2016|
- ITU-T Recommendation G. 823 (1993), The Control of jitter and wander within digital networks which are based on the 2048kbit/s hierarchy.
- ITU-T Recommendation G. 810 (1996), Definitions and terminology for synchronization networks.
- ITU-T Recommendation G. 822 (1998), Controlled slip rate objectives on an international digital connection.
- Huang Haisheng. Design and Implementation of Clock Recovery Circuit E1 in Ethernet [J]. Modern Electronics Technique, 2008, 18:8–10.
- Li Xin, Huang Haisheng, Zhang Bin, Hui Nan. A design for clock data recovery circuit of E1 [J]. Journal of Xi’an University of Posts and Telecommunications, 2012, 17(3):61–72.
- Guo Wei, Chen Xue, Eng Yu, Gai Pengfei. Clock synchronization of E1 over EPON [J]. Study on Optical Communications, 2006, 134(2):10–12.
- Chung Chingche, Le Chenyi. An all-digital phase-locked loop for high-speed clock generation [J], Solid-State Circuits, 2003, 38(2):347–351. [CrossRef]
- Huang Changjiang, Hua Yu, Hu Yonghui. Development of a high-precision time synchronizer and its performance test [J], Journal of Time and Frequency, 2014, 37(1):10–17
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