Open Access
Issue
MATEC Web of Conferences
Volume 40, 2016
2015 International Conference on Mechanical Engineering and Electrical Systems (ICMES 2015)
Article Number 07009
Number of page(s) 4
Section Power electronics engineering
DOI https://doi.org/10.1051/matecconf/20164007009
Published online 29 January 2016
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  2. ITU-T Recommendation G. 810 (1996), Definitions and terminology for synchronization networks.
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  4. Huang Haisheng. Design and Implementation of Clock Recovery Circuit E1 in Ethernet [J]. Modern Electronics Technique, 2008, 18:8–10.
  5. Li Xin, Huang Haisheng, Zhang Bin, Hui Nan. A design for clock data recovery circuit of E1 [J]. Journal of Xi’an University of Posts and Telecommunications, 2012, 17(3):61–72.
  6. Guo Wei, Chen Xue, Eng Yu, Gai Pengfei. Clock synchronization of E1 over EPON [J]. Study on Optical Communications, 2006, 134(2):10–12.
  7. Chung Chingche, Le Chenyi. An all-digital phase-locked loop for high-speed clock generation [J], Solid-State Circuits, 2003, 38(2):347–351. [CrossRef]
  8. Huang Changjiang, Hua Yu, Hu Yonghui. Development of a high-precision time synchronizer and its performance test [J], Journal of Time and Frequency, 2014, 37(1):10–17

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