MATEC Web Conf.
Volume 158, 2018VI International Forum for Young Scientists “Space Engineering 2018”
|Number of page(s)||5|
|Published online||19 March 2018|
High speed video recording system on a chip for detonation jet engine testing
Lavrentiev Institute of Hydrodynamics SB RAS, 630090 Novosibirsk, Russia
* Corresponding author: firstname.lastname@example.org
This article describes system on a chip development for high speed video recording purposes. Current research was started due to difficulties in selection of FPGAs and CPUs which include wide bandwidth, high speed and high number of multipliers for real time signal analysis implementation. Current trend of high density silicon device integration will result soon in a hybrid sensor-controller-memory circuit packed in a single chip. This research was the first step in a series of experiments in manufacturing of hybrid devices. The current task is high level syntheses of high speed logic and CPU core in an FPGA. The work resulted in FPGA-based prototype implementation and examination.
© The Authors, published by EDP Sciences, 2018
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (http://creativecommons.org/licenses/by/4.0/).
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