Warpage behavior analysis in package processes of embedded copper substrates

¹ National Sun Yat-Sen University, Department of Mechanical and Electro-Mechanical Engineering, 80424, Gushan Dist, Taiwan
² Advanced Semiconductor Engineering, 81170 Nanzi Dist Kaifa Rd. No.25, Taiwan

^* e-mail: M043020067@student.nsysu.edu.tw

Abstract

With the advance of the semiconductor industry and in response to the demands of ultra-thin products, packaging technology has been continuously developed. Thermal bonding process of copper pillar flip chip packages is a new bonding process in packaging technology, especially for substrates with embedded copper trace. During the packaging process, the substrate usually warps because of the heating process. In this paper, a finite element software ANSYS is used to model the embedded copper trace substrate and simulate the thermal and deformation behaviors of the substrate during the heating package process. A fixed geometric configuration equivalent to the real structure is duplicated to make the simulation of the warpage behavior of the substrate feasible. An empirical formula for predicting the warpage displacements is also established.