MATEC Web of Conferences
Volume 57, 20164th International Conference on Advancements in Engineering & Technology (ICAET-2016)
|Number of page(s)||4|
|Section||Electronic & Electrical Engineering|
|Published online||11 May 2016|
Design and analysis of 32 bit CMOS adder using sub-threshold voltage at deep submicron technology
1 M-Tech Student, Department of Electronics, Yadavindra college of Engineering, Talwandi Sabo(Pb) - INDIA
2 Parminder Singh, Assistant Professor, Department of Electronics, Yadavindra College of Engineering, Talwandi Sabo
FA is basic cell for arithmetic operation and lots of efforts have put to minimize power consumption and delay. This paper evaluates conventional CMOS adder, bridge style adders in sub-threshold region. Circuits are designed at 20 MHz and 50 MHz frequencies with VDD= 200 mv. All adder designs are simulated at 32 nm technology. In 1 bit and 32 bit conventional CMOS adder design, an efficient trade-off between delay and power is achieved. Experimental results show that 32 bit adder designs have significant improvements in delay and power delay product.
© Owned by the authors, published by EDP Sciences, 2016
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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