Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell

Faculty of Engineering Technology, University Malaysia Pahang (UMP), Lebuhraya Tun Razak, 26300, Pahang, Malaysia

^a Corresponding author: yasirhashim@ump.edu.my
^b hayyan@ump.edu.my
^c sulastri@ump.edu.my

Abstract

This paper represents the impact of nanowires ratio of silicon nanowire transistors on the characteristics of 6-transistors SRAM cell. This study is the first to demonstrate nanowires ratio optimization of Nano-scale SiNWT Based SRAM Cell. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both nanowires ratio and digital voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decreasing in optimization ratio but with increasing in current and power. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower dimensions and lower inflection currents and then with lower power consumption.