Improved Simulated Annealing Genetic Algorithm based Low power mapping for 3D NoC
MATEC Web Conf., 232 (2018) 02022
Published online: 2018-11-19
Articles citing this article
The Citing articles tool gives a list of articles citing the current article.
The citing articles come from EDP Sciences database, as well as other publishers participating in CrossRef Cited-by Linking Program. You can set up your personal account to receive an email alert each time this article is cited by a new article (see the menu on the right-hand side of the abstract page).
Cited article:
This article has been cited by the following article(s):
Thermal-aware application mapping using genetic and fuzzy logic techniques for minimizing temperature in three-dimensional network-on-chip
Farzaneh Asadzadeh, Akram Reza, Midia Reshadi and Ahmad KhademzadehThe Journal of Supercomputing 80 (8) 11214 (2024)
https://doi.org/10.1007/s11227-023-05869-x
A survey on mapping and scheduling techniques for 3D Network-on-chip
Simran Preet Kaur, Manojit Ghose, Ananya Pathak and Rutuja PatoleJournal of Systems Architecture 147 103064 (2024)
https://doi.org/10.1016/j.sysarc.2024.103064
A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC
Khadidja Gaffour, Mohammed Kamel Benhaoua, Abou El Hassan Benyamina and Amit Kumar SinghConcurrency and Computation: Practice and Experience 33 (10) (2021)
https://doi.org/10.1002/cpe.6194
12836 86 (2021)
https://doi.org/10.1007/978-3-030-84522-3_7
Computational Science and Its Applications – ICCSA 2019
Maamar Bougherara, Nadia Nedjah, Djamel Bennouar, Rebiha Kemcha and Luiza de Macedo MourelleLecture Notes in Computer Science, Computational Science and Its Applications – ICCSA 2019 11620 654 (2019)
https://doi.org/10.1007/978-3-030-24296-1_53