MATEC Web of Conferences
Volume 57, 20164th International Conference on Advancements in Engineering & Technology (ICAET-2016)
|Number of page(s)||4|
|Section||Electronic & Electrical Engineering|
|Published online||11 May 2016|
- J. M. Muller, Avoiding Double Roundings in Scaled Newton-Raphson Division, Proceedings of Asilomar Conference on Signals, Systems and Computers, 396-399 (2013)
- I. Kong, E. E. Swartzlander, A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division, IEEE Transactions on Computers 59, 1703-1708 (2010) [CrossRef]
- A. R. Garca, L. P. Escalante, R. P. Michel, O. L. Gandara, J. Cortez, Fast Fixed-Point Divider Based on Newton-Raphson Method and Piecewise Polynomial Approximation, Proceedings International Conference on Reconfigurable Computing and FPGA, 1-6 (2013)
- Peter Malik, High throughput floating-point dividers implemented in FPGA, IEEE conference, (2015)
- A. Rathor, L. Bandil, Design Of 32 Bit Floating Point Addition And Subtraction Units Based On IEEE 754 Standard, International Journal of Engineering Research & Technology 2, 2278-0181 (2013)
- Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics Sixteen Simple Mathematical Formulae from the Veda, (1965)
- A. Kanhe, S. K. Das, A. K. Singh, Design And Implementation Of Low Power Multiplier Using Vedic Multiplication Technique, International Journal of Computer Science and Communication 3, 131-132 (2012)
- A. Ashrafy, M. Salem, A. Anis, An efficient implementation of floating point multiplier, Electronics Communications and Photonics Conference, (2011)
- B. Hickmann, A. Krioukov, M. Schulte, M. Erle, A Parallel IEEE 754 Decimal Floating Point Multiplier, 25th International Conference on Computer Design, (2007)
- IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, (2008)
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