| Issue |
MATEC Web Conf.
Volume 336, 2021
2020 2nd International Conference on Computer Science Communication and Network Security (CSCNS2020)
|
|
|---|---|---|
| Article Number | 02023 | |
| Number of page(s) | 11 | |
| Section | Industrial Design and Engineering Technology | |
| DOI | https://doi.org/10.1051/matecconf/202133602023 | |
| Published online | 15 February 2021 | |
A joint design method of frame synchronization code and LDPC code
College of Information Engineering, Zhengzhou University, 100 Science Avenue, Zhengzhou City, Henan Prov, China
* Corresponding author: iepengsun@zzu.edu.cn
Frame synchronization word (FSW) is an important basis in signal synchronization detection. In our work, the joint design of frame synchronization words and error correcting code are proposed which through regularly distributing the frame synchronization words among the information bits to improve the decoding performance of the LDPC. Frame synchronization word should be added to the information sequence corresponding to the position with the check matrix larger column weight which can guarantee that more Frame synchronization words are received by the check node in the decoding iteration. The frame synchronization word is known to the receiver which play an important role in decoding iteration. The results of simulation show that the algorithm makes an obvious improvement in decoding performance when the signal-noise ratio (SNR) is lower than 1 dB.
© The Authors, published by EDP Sciences, 2021
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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