MATEC Web Conf.
Volume 309, 20202019 International Conference on Computer Science Communication and Network Security (CSCNS2019)
|Number of page(s)||8|
|Published online||04 March 2020|
The advancement of cluster based FPGA place & route technic
1 Smart Shine Microelectronics Technology CO. Ltd, Beijing 10089, China
2 Information & Telecommunications Company. State Grid Shandong Electric Power Company, Jinan 25010, China
* Corresponding author: firstname.lastname@example.org
As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.
Key words: FPGA / Place and route / Cluster structure
© The Authors, published by EDP Sciences, 2020
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