MATEC Web Conf.
Volume 232, 20182018 2nd International Conference on Electronic Information Technology and Computer Engineering (EITCE 2018)
|Number of page(s)||7|
|Section||Network Security System, Neural Network and Data Information|
|Published online||19 November 2018|
A scalable ASIP for BP Polar decoding with multiple code lengths
The Institute of Application Specific Instruction-set Processor, Beijing Institute of Technology, 5 South Zhongguancun Street, Haidian District, 100081, Beijing, China
a Dake Liu: email@example.com@bit.edu.cn
In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.
© The Authors, published by EDP Sciences, 2018
This is an open access article distributed under the terms of the Creative Commons Attribution License 4.0 (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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