MATEC Web Conf.
Volume 208, 20182018 3rd International Conference on Measurement Instrumentation and Electronics (ICMIE 2018)
|Number of page(s)||5|
|Section||Electronics and Communication Engineering|
|Published online||26 September 2018|
An Efficient Hardware-Based Fault-Tolerant Method for SMS4
University of Electronic Science and Technology of China, 611731 West Hi-Tech Zone, China
The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.
© The Authors, published by EDP Sciences, 2018
This is an open access article distributed under the terms of the Creative Commons Attribution License 4.0 (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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