| Issue |
MATEC Web Conf.
Volume 164, 2018
The 3rd International Conference on Electrical Systems, Technology and Information (ICESTI 2017)
|
|
|---|---|---|
| Article Number | 01003 | |
| Number of page(s) | 11 | |
| DOI | https://doi.org/10.1051/matecconf/201816401003 | |
| Published online | 23 April 2018 | |
Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes
Departement of Software Engineering, National Institute of Technology (ITN Malang). Jalan Sigura-gura 2, Malang 65145, Indonesia.
* Corresponding author: amahmudi@hotmail.com
In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.
Key words: FPGA / Hard decision decoding / Reed Solomon Code / Welch Berlekamp algorithm
© The Authors, published by EDP Sciences, 2018
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (http://creativecommons.org/licenses/by/4.0/).
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