Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes

. In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.


Introduction
The introduction of error control codes in data transmission and data communication is due to the addition of unwanted noise over the noisy channel.These error control codes are used to minimize the error.These codes are capable of detecting and correcting errors to achieve minimum error level.
Decoding Reed Solomon codes can be classified into two categories: soft decision decoding and hard decision decoding.The soft decision decoding is quite complex and very hardware intensive to implement.Generalized Minimum Distance Decoding is one example of the soft decision decoding.The hard decision decoder is very popular because it is very simple to implement [1,2].The Berlekamp-Massey Algorithm and the Euclidean Algorithm are the two well-known algorithms to solve the key equation in hard decision decoding [3][4][5].However, the use of the Welch Berlekamp Algorithm to solve the key equation is not much presented [1,6].
RS code is a cyclic linear block code that has been used in many modern applications.Advanced television [7], DVD applications [8], data hiding [9,10] and data transmission with nano satellite [11] are some few applications in our modern life.
This paper presents the hard decision decoding for RS codes RS(63, 59), especially on the VHDL implementation of the Welch Berlekamp algorithm to solve the key equation for RS(63, 59) decoder.
This paper is primarily concerned with the VHDL implementation of the Welch Berlekamp algorithm to decode Reed Solomon Codes over GF (2 6 ), especially RS(63, 59).Some modifications have been carried out on the algorithm so that it is easier to implement.This paper is organized as follows.In section 2, a brief explanation of RS codes is given.Section 3 presents the RS encoder and section 4 deals with the RS decoder.Section 5 and section 6 deal with the implementation and results, respectively.Finally, section 7 is the conclusions.

RS code
The RS code is normally specified as RS(n, k) where n = 2 m 1 and k = n2t are the number of symbols in every codeword and the number of information symbols in every codeword [1,2,4], respectively.It works over GF (2 m ) with m bits per symbol.RS(n, k) is able to correct up to t symbols.Then, d = 2t + 1 is the designed distance n-k is the number of redundancy or parity check symbols.The relation between t and nk can be written as 2t = n-k The RS code can be shown in Figure 1 below.In the case of RS(63, 59), this code works over GF (2 6 ) with 6 bits per symbol.It has 63 symbols in every codeword, where it has 59 information symbols and the rest is four parity check symbols.This code can correct up to two symbols.

R S encoder
The RS(n, k) code, is easily explained by using its special polynomial, called generator polynomial, g(x).The general form of the RS(n, k) generator polynomial is shown in Equation 1, Equation 2, and Equation 3 where b is a non-negative integer selected by the designer.In this paper, it is assumed that b = 0.In the case of RS(63, 59), the generator polynomial g(x) is All valid RS(n, k) code words can be regarded as being polynomials of degree (n-1) over GF (2 m ) which are divisible by its generator polynomial g(x).
Let be the information polynomial to be encoded.The systematic encoding works by multiplying the information polynomial I(x) by x n-k .The result is then divided with g(x) to obtain the remainder polynomial of degree n-k-1.The encoded signal is then formed by subtracting r(x) from I(x)x n-k .It can be written as Equation 4) ) It should be noted that the remainder polynomial is, in fact, the parity check polynomial.This generalized encoding scheme is shown in Figure 2.

RS decoder
The RS decoder has three main stages: Re-Encoder, the Welch-Berlekamp algorithm and Chien Search and Error Evaluation

Re-Encoder
The Re-Encoding [2,4,12,13] is similar to the encoding process.This Re-Encoding process is similar to the syndrome computation process.In the case of RS(63, 59) codes, this Re-Encoding process takes 59 received symbols.It internally generates four check symbols.The re-encoder output will be the mod two addition of four internally generated check symbols and four received check symbol.This is then called the 'parity check' symbol.

Modified Welch-Berlekamp algorithm
Then, if variable J = L( W d ,V d ) -L(Q d ,N d ) is defined.The modification process of Figure 4 above Listing 1 above can be explained as follows:

Line 22
As seen on line 15, the condition on Branch Then L(Q d+1 ,N d+1 ) = L(Q d ,N d ) because of line 21 and also L(W d+1 ,V d+1 ) = L(W d ,V d ) +1 because of line 20.
Hence, the modified Welch Berlekamp algorithm can be shown as on Figure 5 and also on Figure 6.
The Welch Berlekamp algorithm output will be Q(x) and N(x) polynomials, the error locator polynomial and the error evaluation polynomial consecutively.These polynomials are able to correct up to t errors at the received signal.It will correct up to two errors, in the case of Q(x) and N(x) polynomials.Then, the Q(x) polynomial will be solved using a Chien-Search to find the root of Q(x).

Chien search and error evaluation
Chien search [1,3] is then used to find the root of Q(x) polynomial.A Horner's rule is normally used to perform Chien Search (where This process requires at most t multipliers and it takes at most tm clock cycles.In the case of RS(63, 59), this Chien search process requires two multipliers (since, t = 2) and it takes 12 clock cycles to complete the process.However, the Chien search can be modified as follows Define Q l (x) = q l x l for 0 < l  d.Then and it can be shown that This modified Chien search requires d multipliers; however, whatever degree of the polynomial, it only takes m clock cycles.In the case of RS(63, 59), this modified Chien search needs two multipliers, but it only takes six clock cycles, whatever degree of the polynomial.Similar process is applied to the N(x) polynomial.
If Q( g ) = 0 then  g is the root of the error locator polynomial Q(x).Then the error value E g to the symbol s g is given by [1,3].) ( Once the error value E g is found using the Equation ( 9) at location  g , the corrected symbol in that particular position can be found by

Implementation
A VHDL design of RS(63, 59) decoder has been designed and it is then synthesized onto a Xilinx XCV600 device.
How the RS decoder works is explained in the following steps.
Step 1: First of all, the received word is first re-encoded to obtain the remainder (parity check).This step needs nm clock cycles.It takes 63x6 clock cycles for RS(63, 59).
Step 2: The Welch-Berlekamp algorithm to solve the key equation.The output of the Welch-Berlekamp algorithm is Q(x) and N(x) polynomials, the error locator polynomial and the error evaluation polynomial consecutively.
Step 3: Find the roots of Q(x) polynomial using Chien search is the next step.If Q(x) = 0 at a certain location, the N(x) polynomial is then evaluated to find the error value.It is then added to the received symbol using modulo twoaddition to doing the correction.

Results
The resulting RS(63, 59) decoder circuit can do up to two errors corrections.The corresponding FPGA layout is shown below in

Conclusions
The VHDL implementation of the Welch Berlekamp algorithm to decode RS code has been presented.A VHDL design RS(63, 59) has been successfully synthesized on a XILINX FPGA.The RS(63, 59) decoder has been simulated using Modelsim Altera software, and also tested for a number of error patterns.The simulation results show that the decoder works as an error only decoder and can correct up to two errors.