MATEC Web Conf.
Volume 76, 201620th International Conference on Circuits, Systems, Communications and Computers (CSCC 2016)
|Number of page(s)||4|
|Published online||21 October 2016|
Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors
1 STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France
2 LPSC, Université Grenoble-Alpes, CNRS/IN2P3, 53 rue des Martyrs 38026 Grenoble, France
a Corresponding author: firstname.lastname@example.org
This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit accuracy. Correlated Double Sampling (CDS) is performed both in the analog and digital domains to preserve the image quality.
Key words: CMOS Image Sensor / Successive-Approximation-Register ADC / Column-parallel architecture / CDS
© The Authors, published by EDP Sciences, 2016
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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