| Issue |
MATEC Web Conf.
Volume 292, 2019
23rd International Conference on Circuits, Systems, Communications and Computers (CSCC 2019)
|
|
|---|---|---|
| Article Number | 04005 | |
| Number of page(s) | 5 | |
| Section | Signal Processing | |
| DOI | https://doi.org/10.1051/matecconf/201929204005 | |
| Published online | 24 September 2019 | |
NDM: 1-Bit Delta-Sigma Converter with Non-Linear Loop
1 1Centre Tecnològic de Telecomunicacions de Catalunya (CTTC/CERCA), 08860, Castelldefels, Spain
2 2Universitat Politècnica de Catalunya (UPC), 08034, Barcelona, Spain
* Corresponding author: aperez@cttc.es
In this paper we propose to introduce a new processing scheme in the basic loop of a Delta Sigma (ΔΣ) analog-to-digital converter. This processing confers extra gains of the converter over both the quantization error and the channel noise. This is an advance with respect to all cases found in the literature, where the desired signal is not protected against channel noise. Also, the proposed processing is simple and contrasts with the existing architectures, which produce better quality at the expense of sensitivity to implementation imperfections due to the presence of multiples loops in the corresponding architecture. Furthermore, the in-phase/quadrature components structure of a band pass signal has not been used to improve the performance of ΔΣ converters.
© The Authors, published by EDP Sciences, 2019
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