MATEC Web of Conferences

FPGA Accelerating Core Design Based on XNOR Neural Network Algorithm

Su Yi, Hu Xiao and Sun Yongjie

MATEC Web Conf., 173 (2018) 01024

Published online: 19 June 2018

DOI: 10.1051/matecconf/201817301024

Su Yi

Hu Xiao

Sun Yongjie

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