Open Access
Issue
MATEC Web Conf.
Volume 188, 2018
5th International Conference of Engineering Against Failure (ICEAF-V 2018)
Article Number 05005
Number of page(s) 8
Section Fault Detection and Reliability in Cyber-Physical and Industrial Systems
DOI https://doi.org/10.1051/matecconf/201818805005
Published online 07 August 2018
  1. D. De Guglielmo, S. Brienza, and G. Anastasi, “IEEE 802.15.4e: A survey,” Comput. Commun., vol. 88, pp. 1-24, Aug. 2016. [CrossRef] [Google Scholar]
  2. Z. Shelby, K. Hartke, and C. Bormann, “The Constrained Application Protocol (CoAP),” Jun. 2014. [Google Scholar]
  3. M. R. Palattella, N. Accettura, X. Vilajosana, T. Watteyne, L. A. Grieco, G. Boggia, and M. Dohler, “Standardized Protocol Stack for the Internet of (Important) Things,” IEEE Commun. Surv. Tutorials, vol. 15, no. 3, pp. 1389-1406, 2013. [CrossRef] [Google Scholar]
  4. E. Aras, G. S. Ramachandran, P. Lawrence, and D. Hughes, “Exploring the Security Vulnerabilities of LoRa,” in 2017 3rd IEEE International Conference on Cybernetics (CYBCONF), 2017, pp. 1-6. [Google Scholar]
  5. A. Fournaris, L. Pocero Fraile, and O. Koufopavlou, “Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: a Survey of Potent Microarchitectural Attacks,” Electronics, vol. 6, no. 3, p. 52, Jul. 2017. [CrossRef] [Google Scholar]
  6. M. Antonakakis, T. April, M. Bailey, E. Bursztein, J. Cochran, Z. Durumeric, J. Alex Halderman, D. Menscher, C. Seaman, N. Sullivan, K. Thomas, and Y. Zhou, “Understanding the Mirai Botnet,” Proc. 26th USENIX Secur. Symp., pp. 1093-1110, 2017. [Google Scholar]
  7. A. P. Fournaris and D. M. Hein, “Trust Management Through Hardware Means: Design Concerns and Optimizations,” in VLSI 2010 Annual Symposium, vol. 105, N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, and M. Huebner, Eds. Springer Netherlands, 2011, pp. 31-45. [CrossRef] [Google Scholar]
  8. R. B. Aussel J D A Sailer, “Only hardware-assisted protection can deliver durable secure foundations,” IEEE Softw., vol. 28, no. 2, p. 57+58-59, 2011. [Google Scholar]
  9. S. Mangard, E. Oswald, and T. Popp, “Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security),” Feb. 2007. [Google Scholar]
  10. T. C. Group, “TPM v2.0 Library Specification,” 2014. [Google Scholar]
  11. A. Fournaris, K. Lampropoulos, and O. G. Koufopavlou, “Trusted Hardware Sensors for Anomaly Detection in Critical Infrastructure Systems,” in in proc. of the 7th International Conference on Modern Circuits and Systems Technologies (MOCAST) on Electronics and Commuications 2018, 2018. [Google Scholar]
  12. D. Challener, K. Yoder, R. Catherman, D. Safford, and L. Van Doorn, A practical guide to trusted computing. IBM press, 2007. [Google Scholar]
  13. T. Alves and D. Felton, “TrustZone: Integrated hardware and software security,” ARM white Pap., 2004. [Google Scholar]
  14. Q. Ge, Y. Yarom, D. Cock, and G. Heiser, “A survey of microarchitectural timing attacks and countermeasures on contemporary hardware,” J. Cryptogr. Eng., pp. 1-27, 2016. [Google Scholar]
  15. D. Gruss, “Software-based Microarchitectural Attacks-PhD Defense,” no. June, 2017. [Google Scholar]
  16. D. A. Osvik, A. Shamir, and E. Tromer, “Cache Attacks and Countermeasures: The Case of AES,” in Proceedings of the 2006 The Cryptographers’ Track at the RSA conference on Topics in Cryptology, Springer-Verlag, 2006, pp. 1-20. [Google Scholar]
  17. Y. Yarom and K. Falkner, “Flush + Reload : a High Resolution, Low Noise, L3 Cache Side-Channel Attack,” USENIX Secur. 2014, pp. 1-14, 2014. [Google Scholar]
  18. F. Liu, Y. Yarom, Q. Ge, G. Heiser, and R. B. Lee, “Last-level cache side-channel attacks are practical,” Proc.-IEEE Symp. Secur. Priv., vol. 2015-July, pp. 605-622, 2015. [Google Scholar]
  19. G. Irazoqui, M. S. Inci, T. Eisenbarth, and B. Sunar, “Wait a minute! A fast, cross-VM attack on AES,” Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics), vol. 8688 LNCS, no. Vmm, pp. 299-319, 2014. [Google Scholar]
  20. G. Irazoqui, T. Eisenbarth, and B. Sunar, “Cross Processor Cache Attacks,” Proc. 2016 ACM Asia Conf. Comput. Commun. Secur., pp. 353-364, 2016. [Google Scholar]
  21. N. Zhang, K. Sun, D. Shands, W. Lou, and Y. T. Hou, “TruSpy : Cache Side-Channel Information Leakage from the Secure World on ARM Devices,” Cryptol. ePrint Arch. Rep. 2016/980, 2016. [Google Scholar]
  22. M. Lipp, D. Gruss, R. Spreitzer, C. Maurice, and S. Mangard, “ARMageddon: Cache Attacks on Mobile Devices,” in Proceedings of the 25th USENIX Security Symposium, pp. 549-564, Austin, TX, US, 2016. [Google Scholar]
  23. X. Zhang, “Return-Oriented Flush-Reload Side Channels on ARM and Their Implications for Android Security,” CCS ’16 Proc. 2016 ACM SIGSAC Conf. Comput. Commun. Secur., pp. 858-870, 2016. [CrossRef] [Google Scholar]
  24. P. Kocher, D. Genkin, D. Gruss, W. Haas, M. Hamburg, M. Lipp, S. Mangard, T. Prescher, M. Schwarz, and Y. Yarom, “Spectre Attacks: Exploiting Speculative Execution,” Jan. 2018. [Google Scholar]
  25. M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas, S. Mangard, P. Kocher, D. Genkin, Y. Yarom, and M. Hamburg, “Meltdown,” Jan. 2018. [Google Scholar]
  26. S. Bhattacharya and D. Mukhopadhyay, “Curious case of Rowhammer: Flipping secret exponent bits using timing analysis,” Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics), vol. 9813, pp. 602-624, 2016. [Google Scholar]
  27. D. Gruss, C. Maurice, and S. Mangard, “Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript,” 2015. [Google Scholar]
  28. V. Van Der Veen, Y. Fratantonio, M. Lindorfer, D. Gruss, C. Maurice, G. Vigna, H. Bos, K. Razavi, and C. Giuffrida, “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms,” in CCS, 2016. [Google Scholar]
  29. E. Bosman, K. Razavi, H. Bos, and C. Giuffrida, “Dedup Est Machina: Memory Deduplication as an Advanced Exploitation Vector,” Proc.-2016 IEEE Symp. Secur. Privacy, SP 2016, pp. 987-1004, 2016. [CrossRef] [Google Scholar]
  30. M. Seaborn and T. Dullien, “Exploiting the DRAM rowhammer bug to gain kernel privileges How to cause and exploit single bit errors Mark Seaborn and Thomas Dullien Bit flips !” [Google Scholar]
  31. T. Zhang and R. B. Lee, “Secure Cache Modeling for Measuring Side-channel Leakage,” pp. 1-27. [Google Scholar]

Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.

Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.

Initial download of the metrics may take a while.