MATEC Web Conf.
Volume 128, 20172017 International Conference on Electronic Information Technology and Computer Engineering (EITCE 2017)
|Number of page(s)||8|
|Section||Simulation Model and Algorithm|
|Published online||25 October 2017|
Research on Fault Tolerance Enhancement of Array Erasure Codes
Software Engineering Institute, Chengdu University of Information Technology, 610225 Chengdu, P. R, China
a Corresponding author: email@example.com
Array erasure coding technology is one of the most desirable methods to enhance the reliability of storage systems, but fault tolerance is always the bottleneck to the use of array codes. There are several improvement schemes for fault tolerance of array codes now, such as graph theory method, hybrid layout method, and so on. But improvement of the fault tolerance is pretty small, and always cost too much. In view of this, the paper presents a new method to improve fault tolerant ability of array erasure codes. The new method has a highly computing efficiency because all calculations are binary XOR operations, and it is convenient to implement because of its simple construction. Using this new method, we can model a horizontal array code with the optimal updating expenses. Although MDS array codes cannot be modeled by the new method, but storage efficiency can be improved by increasing the strip size. The most important contribution of this paper is that, this new method can construct an array erasure code which has the unconstrained fault tolerant ability in theory.
© The authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (http://creativecommons.org/licenses/by/4.0/).
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