A large gain variable range, high linearity, lownoise, low DC offset VGAs used in BD system

In this paper, a large gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB variable circuit are introduced. In the VGAs chain, the last and the first VGAs employ Bipolar transistors, to improve the linearity and noise characteristics. And the middle three stages VGAs employ MOS transistors. The whole circuitry is designed in 0.35um BiCMOS process, including variable gain amplifiers (VGAs) , fixed gain amplifiers , gain control and DC offset cancellation parts. The automatic gain control loop (AGC) provides a process independent gain variable range of 60dB (including 50dB gain-dB-linearity variable range), with a 200us loop lock time, the VGAs provide a 73dB largest gain, the THD is less than 1% at a 1V(P-P) output level; the equivalent output integral noise is 0.011v/ hz@20MHz bandwidth. The whole area is 1173um*494 um, and the power is 7.1mA at 3.3V signal supply voltage.


Introduction
VGAs are kinds of circuits that are very common in analog system. They are widely used in CCD, disk [1][2] [3] , acoustics [4][5] , detector [6] [7] and communication systems [8] [9] [10] . In communication systems, almost all type of RF frond end receivers need VGAs. And the VGAs are normally employed in a feedback loop to implement an automatic gain control amplifier. Fig.1 gives a kind of applications of VGAs in communication systems. However, all these systems which need VGAs have the same characteristic: the signal is weak and the signal power varies in a wide range.
Normally, there are several parameters of VGAs such as: gain variable range, dc offset rejection, gain control precision need to be carefully considered. For example: in the disk systems, the VGAs must have controllable gain range of 30dB [1] . In GPS systems, to consider all the uncontrollable factors a 40dB gain range is enough [11] . But in the BD system a more than 60dB gain range is needed. Also there are many other characteristics such as: gain -dB -linearity variable, low noise, high linearity, short loop lock time( if there is a AGC loop) need to be thought. In the second part we will discuss these characteristics. Now there are two focuses in VGAs application-field-the gain-dB-linearity variable circuit and the digital vgas. As we know, the CMOS process is becoming the mainstream technology. But in CMOS technology, the gain-dB-linearity variable circuits cannot be realized directly. So there are many methods: pseudo-exponential [12] , various Taylor series approximation [13][14] [15][16] are used to realize a exponential function. No matter which method to choose, all these realizations are aimed at improving the gain variable range in a dB mode with the control voltage. Also in recent years, since the DSP technology has gotten great development. And people begin to use DSP technology to realize traditional VGAs (in this case, VGAS usually are called PGAs: programmable gain amplifiers). To PGAs, the gain can change in any way, so the gain-dB variable circuits are not a problem. But the PGAs cannot give continuous variable gain, the designers optimize the gain discretely only. That may be a question in some systems.
In this paper, a large gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB-linearity variable circuit are introduced. In the second part, several important characteristics are discussed; in the third part, the VGAs , AGC and the gain-dBlinearity variable circuits are referred; in the fourth part the layout and test results are given; in the final part, a conclusion is made.

The system design consideration
In the BD system, several parameters need to be carefully considered. The first one is the gain variable range. Not like other satellite navigation systems, the signal of BD systems has a wide variable range, so the VGAs must give a large controllable gain variable range to keep the output of IF signal at a fixed level (to alleviate the requirement of the ADC). But it is a challenge to supply a large gain variable range without cascade too many VGAs. Furthermore, the frequency of the IF signal is larger than 50MHz, so, too many cascaded VGAs will destroy the bandwidth. Just as Fig 2 displays the signal coming from the antenna may change 20dB and the gain of the RF Frond End circuits may vary 40dB. So, to consider all these possible factors of the system, the gain variable range should not be less than 60dB.
The second parameter is the high linearity. In all communication systems, distortion is the most important factor. The larger the signal levels, the larger the distortion becomes .So, to get less distortion, the signal level must be small. But in BD system, the largest signal get to the antenna is nearly -60dBm, the VGAs must keep a low distortion to insure that the baseband can calculate data correctly. In the design, a 1% THD is required when the output level of the VGAs are 1V (P-P).
The third important factor is low DC offset. To think about that the largest gain of the VGAs is about 73dB, the DC offset of the VGAs must be small or the following circuits of VGAs, even the VGAs themselves will be saturation. In the design, we employ two kinds of circuits to cancel the DC offset: a low pass filter and a large DC offset capacitor. As the MATEC Web of Conferences 355, 03050 (2022) ICPCM2021 https://doi.org/10.1051/matecconf/202235503050 measurement proved that a low pass filter to decrease the offset that produced by the VGAs themselves is necessary.
The fourth factor is the loop lock time. The VGAs of the BD system used in a negative feedback loop, and the system requires the loop lock time must less than 1ms. To consider that the AGC loop should keep stabling under a more than 73dB largest gain so the capacitor of the loop must be large. But to get a short loop lock time, the capacitor should be small. However, when design a AGC loop one have to compromise between stabling and loop lock time. The requirements of the system are summarized in Table.1.

The design of the VGAs chain
The block diagram of the AGC loop is depicted in Fig. 3. It includes three cascaded VGAs and a fixed gain buffer. The output of the fixed gain buffer is a full-wave rectified circuit, though a comparator and a dB-linearity circuit the gain-control voltage is filtered by a big capacitor. And to cancel the DC offset of VGAs themselves, a DC rejection circuits is designed, to cancel the DC offset coming from the frond circuits, a DC capacitor are also employed in the chain of the VGAs.
In the VGAs chain, the last and the first VGAs employ Bipolar transistors, to improve the linearity and noise characteristics. And the middle three stages VGAs employ MOS transistors. All the VGAs have the same architecture, in the following part we will introduce.
In the feedback loop, we design a DAC, so one can choose though the AGC or by the DAC to change the gain of the VGAs chain.

The circuit realization of VGA
VGA is the core of an AGC loop. There are many prevailing VGA designs, and we can commonly group them into two types. One is to control the transconductance of the input transistors to change the gain, the other is to change the load of the VGA to change the gain. A great many circuitry realizations for analog VGAs also exist [2] , and one of them is the use of analog Gilbert-multiplier cell [16] . The Gilbert-multiplier cell can provide wide bandwidth and excellent linearity characteristic. Fig.4 shows such a Gilbert cell in our VGA design. In Fig. 4, the gain of the VGA is controlled by the bias current source. When the difference between Vcontrol1 and Vcontrol1 is small, the gain of the Gilbert-multiplier cell is little; otherwise the gain of the VGA is large. The gain of the VGA can be written as: (1) where the gm+ and gm-are the transconductances of the input transistors.

The circuit realization of the dB-linearity
In communication system, especially when the input signal variable in a wide range, such system need a gain-dB-linearity characteristic. In other words, these systems require a fixed loop settling time. Just take the BD system for an example to illustrate why these system need a gain-dB-linearity circuits to realize a fixed loop settling time.
In BD system, the signal coming from the antenna varies in a large range. So the settling time of the ACG loop will varies in a wide range. As we know, in satellite navigation system, signal amplitude acquisition during a preamble where the data is transmitted. The preamble duration should exceed the acquisition or settling time of the AGC loop. And its duration should be minimized for efficient use of the channel bandwidth. If the AGC circuit is designed such that the acquisition time is a function of the input amplitude, then the preamble is forced to be longer in duration than the slowest possible AGC circuit acquisition time. Consequently, to optimize system performance, the AGC loop settling time should well defined and signal independent.
The relation between gain-dB-linearity characteristic and a fixed loop settling time is a complicated issue. If we build a model of the whole AGC loop, and let the loop settling time independent of the signal amplitude then we will get a interesting conclusion: that the gain of the VGAs and the gain control voltage have a exponential function (2) . Readers who are interested in that may study reference [17][18] .

A(v) = exp ୡ୭୬୲୰୭୪
(2) In this paper, we use Taylor series to approximate the exponential. As we know, in (3) when x<<1, we can approximate the exponential function with the front several terms.
(3) The designed dB-linearity circuit is depicted in Fig. 5. Through these circuits we can get nearly 50dB gain variable range in a dB-linearity mode by four stage VGAs.  Fig.6 is the feedback control circuit. FWR-Sig is the output of the Voltage follower, Vref is a constant voltage level. The difference between FWR-Sig and Vref decide the signal amplitude of the AGC. The amplitude of the output of the AGC can be described: Which A is amplitude of the output signal of the VGAs. In Fig.5 the total currents through M1, M2 are constant. The control voltages are the gates bias voltages Of M3 and M4. If the currents through the two transistors are equal, then the gain of the VGA is zero. Else if more current through M3 or M4, the gain of VGA will become larger. When the amplitude of the output signal meets the requirement of formula (4), the currents through M3 and M4 in Fig.6 will be constant, the whole AGC circuits get to a steady state.

The design of AGC circuits
(4) Fig. 6. The architecture of the full-wave-rejection circuits. Figure 7 is the picture of the whole RF Frond End Receiver. The layout of the whole AGC loop is depicted in Fig. 8. Because the IF is more than 50MHz, the layout should be compacted to reduce the parasitic capacitors and resistors. Fig. 9 is the picture of the evaluation kit. The linearity characteristic of the VGAs is depicted in Fig. 10. As Fig.10 shows, even the signal level getting to the VGAs is -27dBm, the VGAs can correctly amplify the signal. Fig.  11 gives the frequency response of the VGAs. Fig.12 gives the gain dB-linearity variable range. Fig.13 gives the input noise density of the whole loop. Due to the first VGA employing bipolar transisitors, the input noise density is less than 4nV/sqrt(Hz).

Conclusion
In this paper, a high gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB variable circuit is introduced. The whole AGC loop has been used in the Bei Dou RF Frond End receiver. Test results show that the loop suits the system requirements.