Simulation Study of Overcurrent Turn-off Capability in 4500V IGBT

According to the requirement of IGBT's over-current turn-off capability, this paper analyzes the factors affecting the dynamic latch-up of IGBT chip during the over-current turn-off process, including the gate width of IGBT cell, the doping concentration of back P + collector and the dVce/dt when the IGBT is turned off. The simulation results show that the anti-dynamic latch-up capability of IGBT can be effectively improved by decreasing the gate width and back P + collector doping concentration. Through multi-cell parallel simulation, it is found that current concentration exists in the process of overcurrent trun-off, which leads to the further increase of the lattice temperature, and the overcurrent turn-off capability declines.


Introduction
In the new generation of high-power self-turned-off power electronic devices, IGBT (Insulated Gate Bipolar Transistor) devices have become the preferred devices in power electronic equipment. As an important application scenario of high-voltage IGBT devices, flexible-HVDC(High Voltage direct current) transmission technology has the advantages of independent control of active and reactive power, rapid regulation, and realization of large-scale power distribution, etc. It has broad prospects for development in large-scale renewable energy access, island power supply and new urban power grid construction [1] . As one of the core components of flexible-HVDC transmission, the high-voltage DC circuit breaker puts strict requirements on the IGBT device. The IGBT device needs to withstand 2~5ms duration, peak current equals to six times the rated current, and turn-off safely [2] .
In this paper, the cell of 4500V IGBT chip is taken as the research object. Firstly, the factors affecting the overcurrent turn-off capability of IGBT chip are analyzed theoretically, including the width of gate, P-well doping concentration and back P+ doping concentration. Secondly, the cell structure model and device characteristics simulation model of IGBT are established in the Sentaurus-TCAD. The influence of each parameter is simulated and analyzed to guide the structure design and development of 4500V IGBT chip with high turn-off capability.

Turn-off behavior of IGBT
In the case of flexible-HVDC transmission, the load of IGBT device is inductive load, and the schematic diagram of working circuit is shown in Fig.1, this is a typical clamped inductive application. Ls is the stray inductance of the circuit, LLoad is the load inductance, FRD (Fast Recovery Diode) is the freewheeling diode in the IGBT turn-off process, Vge is the gate driving voltage of IGBT, generally a gate driving resistance Rg is connected between the driving power supply and IGBT gate, Vcc is the power supply voltage. During clamped inductive turn-off transient, the stray capacitance in the IGBT play an important role in determining the turn-off behavior. The stray capacitance of IGBT consists of three parts, Cce is the collectoremitter capacitance, Cge is the gate-emitter capacitance, and Cgc is the gate-collector capacitance. Cgc consists of two parts, including oxide capacitor Cox and PN junction depletion layer capacitance Cdep.
The turn-off process of IGBT can be divided into four parts, as shown in Fig.2. All the four parts are as follows.
Part (1): When the turn-off signal is applied, the gateemitter capacitance Cge and Miller capacitance Cgc begin to discharge. The gate-emitter voltage Vge falls down to a plateau and remains constant until the completion of the well-known Miller-effect [3] . In this part, since the FRD is still reverse biased, the load current IL can not divert into the diode. The collector-emitter voltage Vce and collector current Ic remain at their steady values. In the end of this part, the depletion layer slightly expanded, resulting in a slight increase in Vce [4] .
Part (2): When Vce increases few volts, the part 2 starts. At this time, Vce increases rapidly, the depletion region in the N-base begins to expand. This results in a great reduction of the depletion capacitance Cdep. Consequently, the Miller capacitance Cgc reduces to a much smaller value. After that, the gate drive only discharges the capacitance Cge, the Vge then decreases towards Vge off. In this part, the load current cannot divert into the FRD. However, due to the large dV/dt at the anode side, the diode can still share a small part of load current. The IGBT current Ic then undertakes a slow decreasing.
Part (3): When Vce reaches to Vcc, the part 3 starts. The Vge falls below the threshold voltage Vth, the MOS electron current and the hole drift current associated with it are removed. This results in an initial rapid fall of Ic. Meanwhile, Vce further increases by an amount equal to the voltage drop across the stray inductance LS, which is well known as voltage overshoot of Vce.
Part (4): When the Vce falls back to Vcc, the part 4 starts. In this period, the Vce approximately remains constant. The collector current Ic undertakes a slow decreasing due to the remaining excess carrier recombination in the undepleted n-base region and n+ buffer layer.

Influence factors of IGBT overcurrent turn-off capability
During the over-current turn-off of IGBT chip, the current Ic remains at a higher level during the part 3, when the channel is closed and the current is all hole current. The hole concentration in the space charge region is given by equation (1).
The positive charge determined by the distribution of electric field inside the space charge is given by equation (2).
From equation (2), it can be seen that the positive charge is greater than the intrinsic donor concentration during the turn-off process, which enhances the electric field of PN junction between P-well and n-base region, resulting in the decrease of breakdown voltage of the device, and this change is more obvious with the increase of the turn-off current. In this process, because all the current is hole current, the hole current density under the N+ source region is increased, and the latch-up condition is easy to trigger and the dynamic latch-up occurs. Since there is no electronic current component, the hole current injected by P+ collector becomes uniform in the device profile, so the criterion of dynamic latch-up can be determined as follows (3), and (4) ~ (7) gives the calculation formulas of each physical quantity. Vbi is the built-in potential of PN junction between N+ source region and p-well, which is about 0.7V at 125℃ and decreases gradually with the increase of temperature. The structure and parameters of IGBT are shown in Fig.3   It can be seen from the expression that the increase of dVc/dt leads to the decrease of the turn-off current density during the turn-off process, and the change rate of collector voltage can be reduced by changing the gate drive resistance, but the turn-off loss can be increased. In terms of cell structure, enlarging gate width or reducing the emission efficiency of the back collector and the amplification ratio of the common base of the transistor can improve the current turn-off capability, but the effect of the reduction of the back collector injection efficiency on the Vce(sat) and short circuit capability should be considered. At the same time, the dynamic latch-up of IGBT can be restrained by reducing the resistance of Pwell and P+, but it will bring adverse effects on the threshold voltage, so it needs to be carefully dealt with in the design.
In practice, IGBT chip is made up of large-scale cells in parallel. Due to the uneven distribution of current and the concentration of current during the turn-off process, some cells will withstand high current density during the turn-off process [6] , resulting in high temperature locally, causing latch-up and chip burnout.

Simulation Results
The simulation analysis is carried out in the software of Sentaurus-TCAD. The mixed-mode of SDEVICE module is used to build the simulation circuit，each part of the circuit refers to the Fig.1. IGBT is generated by SPROCESS module, Vcc=3600V, Ls=6uH, LLoad = 1mH, Vge on=+19V, Vge off = -15V, Rg=47ohm. The chip area is set to 1cm 2 and the rated current is about 60A, and the turn-off current value is set to 400A. We will compare the maximum lattice temperature to determine the risk of dynamic latch-up. Fig.4 shows that the maximum lattice temperature varies with the doping concentration in the back P+ collector region. When the concentration increases, the hole concentration in the n-base region injected from the collector region increases, and the hole current density increases during the turn-off process, resulting in the increase of the lattice temperature and the risk of dynamic latch-up. Fig.5 shows the maximum lattice temperature varies with the change of gate width, when the gate width increases, the channel density decreases when the chip area and turn-off current are constant, and the hole current density in the P-well region increases during the turn-off process, which results in the increase of lattice temperature and the risk of dynamic latch-up.   In order to verify the actual situation of the chip, the multi-cell structure is simulated. The simulation results of different cell numbers are given in Fig.6. With the increase of the number of simulated cells, the maximum temperature of the lattice increases gradually. The main reason for this result is that the current distribution is not uniform during the turn-off process, and the current density of some cells is greatly increased. The current density distribution of 16 cells at one time point during the turn-off process is given in Fig.7. It can be seen that the current density of 6 cells in the middle is significantly higher than others.

Conclusion
Based on the theoretical analysis of the hole current in the IGBT turn-off process, the main cell structure parameters affecting the dynamic latch-up of the IGBT are P-well doping concentration, P+ doping concentration, gate width, back P+ collector doping concentration and so on.
The simulation results show that by reducing the gate width and back P+ collector doping concentration, the local lattice temperature rise of IGBT can be effectively reduced and the overcurrent turn-off capability of IGBT can be improved. From the simulation results of cell parallel connection, the current concentration during the cell parallel and the maximum lattice temperature are further increased. In the future, this phenomenon needs to be deeply simulated and analyzed.