Design of Oscillator Based on A Deformed Structure Parallel Coupled Line Filter

This paper proposes an oscillator based on a deformed structure parallel coupled line filter design. The requirements of this design are the output power meet 10dBm, and phase noise is below -90dBc/Hz at 10kHz off the centre point. This work adopts parallel positive feedback form, and it use Parallel Coupled Line Filter, making this design simple in structure and low in cost. This design has low phase noise and high output power features, working at 2.4GHz, intended to use in a through-the-wall radar system.


Introduction
As an important part of microwave circuit system, the oscillator is one of the most exploited and ubiquitous modules in Radio Frequency Integrated Circuit (RFIC) systems which have to comply with stringent requirements. And its performance often determines whether the entire system will meet specifications or not. Output power, phase noise and harmonic suppression are critical parameters of an oscillator [1].
Oscillators are normally comprised of two distinct sections, namely, the active section, and the resonator, which a device that naturally oscillates at a certain frequency. There are many kinds of resonator, for example, LC tank, crystal, surface acoustic wave, yttrium iron garnet and dielectric resonators. In many studies, parallel coupled line filters have been widely used due to their simple structure and low cost. In recent years, substrate integrated waveguides with higher Q values have also attracted the attention and application of many scholars. And many research working on the low phase noise oscillators and their behavior has been down [2][3][4][5].
When the software ADS is used for schematic simulation, its results are under ideal original conditions, which is different from the actual one. The electromagnetic simulation (EM simulation) compares the layout of the analog circuit on the dielectric substrate and the result of the component package with parasitic parameters to obtain simulation data that is closer to the actual situation.
This paper proposes an oscillator which has low phase noise and high output power, working at 2.4GHz, intended to use in a through-the-wall radar system. And this paper will introduce the design of the oscillator from two aspects, low noise amplifier and parallel coupled line filter. Then analyze the results of EM and schematic co-simulation and discuss about the results of it.

Design of oscillator
Parallel feedback oscillators are based on positive feedback system. Part of the transistor output signal is fed back to the transistor input end through the feedback loop. When this part of signal is in phase with the transistor input signal, the oscillating circuit works in positive feedback state. When satisfying certain starting conditions and maintaining oscillation conditions, the output of the transistor will produce a stable output signal. The schematic diagram of parallel feedback oscillator is shown in Figure 1.  represents a ratio of vf to v0, which is the transmission coefficient of the feedback network.
As for parallel feedback oscillators, according to Barkhausen Criterion, we must ensure that the loop is a positive feedback state and the whole loop gain is 1.
Based on the above analysis, we can draw a conclusion [6]:

Low noise amplifier
Since the designed oscillator needs higher output power, considering Field Effect Tube(FET) has better noise factor but lower max gain, this work chooses Bipolar Junction Transistor(BJT) BFP520 to implement active amplifier part. By consulting the datasheet of BFP520, this work adopts co emitter structure, setting the Bias point at 2 , 20 In order to make the transistor work steadily and in the state of amplify, this work verifies the stability factor K working at above Bias point by following formulate [7].
The next step is to match input and output impedance. In order to make the load absorb the maximum power, the input and output terminals are both conjugate matched. However, in order to reduce the phase noise, the matching of the input ends is based on the minimum noise impedance matching, matching input impedance in Z of the LNA to Conjugate source impedance * s Z , by entering matching network.
And the matching of the output ends is based on the maximum gain impedance matching. The schematic diagram of impedance matching is shown as figure2.  The initial length of the upper and lower stubs was set to be equal to a quarter of the wavelength. The appropriate initial value of the filter size could be easily determined from the approximate analytical equation [9].  And i g was the element value of low-pass filter prototype. In [10], several methods for reducing phase noise were given: (1) The transistor was selected with a lower flicker noise corner frequency c f . (2) The resonator was selected with a higher unloaded Q value as the frequency selection original.
(3) The transistor was chosen with a lower noise figure.
(4) The transistor was try to avoid working in saturation when designing the oscillator.

Simulation of bias circuit
The proper bias point of transistor is set according to transistor datasheet. This paper calculate approximate resister value and use simulate software ADS to generate bias circuit. And the stability factor K should be verified above 1 around centre frequency. In this work, K is above 1 in the pass band, so there is no need to add feedback inductor on the emmitor of the transistor. And this paper adopt co emitter structure, setting the Bias point a

Simulation of impedance matching
Impedance match on input terminal and output terminal is implemented after the transistor working at proper bais point. There are two ways to implement impedance matching, one is matched by the load to the source impedance; the other is matched by the source impedance to the load impedance. This paper uses the first matching method. In order to reduce the influence of phase noise, the minimum noise matching is used at the input matching end, that is, the impedance value of the system at the minimum noise figure is used as the input impedance of the low noise amplifier. While in order to achieve high output power, the maximum gain matching is used at the output of the low noise amplifier, that is, the impedance value of the theoretical maximum gain at the selected bias point is used as the output impedance, and the load impedance 50  is matched to the conjugate of the output impedance. The impedance matching simulating result is shown in figure 5,   Considering that the 2.4G wavelength is long, in order to reduce the board size, this paper adjusts the filter to the form of Figure 7. In order to reduce the coupling between the micro strip lines, the micro strip line spacing is adjusted to twice the line width according to experience.   Then this paper implements co-simulation using closed-form electromagnetic and harmonic balance techniques applied to the circuit board and active circuit, respectively.

Results of oscillator simulation
The schematic of co-simulation is shown in figure 10.

Figure 10. Schematic of EM and schematic co-simulation
The frequency sweep range is set from 1.5GHz to 3GHz. The simulation results are shown in figure 11. As the results showed above, the output power is 11dBm, considering machining error. And the phase noise is -173.26 dBc/Hz at 10kHz off centre point, which was better than -88 dBc/Hz in [1]; and the phase noise was -177.45dBc/Hz, which was better than -102 dBc/Hz in [6] and -103dBc/Hz in [10] with the use of substrate integrated waveguide(SIW).
The results meet design requirements, with a standard sine wave outputting.

Conclusion
This paper proposed an oscillator based on a deformed structure parallel coupled line filter design, and the size of the circuit board was 40mm*40mm. The design results meet the design specifications and leave a margin.
This design can be used in designs such as throughwall radars that require high output power and low phase noise.