Design , Simulation and Validation of HMC 833 Loop Filter Based on Matlab

In the light of the complexity of the conventional research and design of HMC833 wideband PLL, this paper studies a design method of HMC833 loop filter based on Simulink modeling in Matlab. The dynamic parameters of loop response, such as maximum overshoot, regulation time and steady-state error, are analyzed to verify the feasibility of HMC833 loop filter design.


Introduction
High temperature ceramic sensor detection system based on FPGA control needs to use FPGA as the master chip to control the high frequency signal of 5.42GHz-5.5GHzproduced by the HMC833 chip.Then the high temperature ceramic passive wireless sensor is used for feedback collection to obtain the reflected resonant frequency, and then the real-time temperature is obtained by the relationship between resonant frequency and temperature parameters.Finally, the time curve of the resonance frequency, the real-time temperature, the S11 waveform and the temperature are displayed on the touch screen.
In order to ensure the stability of HMC833 chip to send 5.42GHz-5.5GHzhigh frequency signals, broadband PLL is used to lock frequency.

Principle of HMC833
The HMC833 chip uses a surface mount package with 40 pins, including power and ground pins, signal control pins, high frequency signal pins, low frequency signal pins, and idle pins.From the Figure 1,you can see the HMC833 internal resources and function of each module.
The external reference clock is brought into the chip by the pin XREFP.The pin CP turns the error signal of the discriminator into a current pulse, and then outputs it to an external loop filter.The filtered signal enters the on-chip VTUNE from the pin VCO.Finally, the VCO outputs a high frequency signal [1] by the pin RF-OUT through a programmable frequency division doubler.The external control signal is written to the internal registers of the chip through three pins of SEN, SDI and SCK.The pin LD-SDO can not only configure the locked output of the PLL, but also output the value of the internal register.CEN is the chip enable port, active high level.The BIAS decoupling for bias circuits requires the series connection of a capacitor to ground.

Phase-locked loop
The charge pump phase locked loop is an automatic controlled closed-loop negative feedback system.It automatically tracks the phase and frequency of the input signal.The phase of the output signal can also be locked.The principle of automatic control is its theoretical basis.

Design of loop filter
The higher order loop filter model is evolved from the two order model.It adds two stage capacitor resistance combinations at the back of the 2 order model [2].In the actual circuit, the first two stage filter plays a major role in the parameters of PLL, loop bandwidth, damping coefficient and phase noise.In contrast, the third and fourth stage filters in the back end are designed to optimize phase noise and improve output performance.The Simulink model in Matlab is shown in Figure 3.
The quality of the loop filter directly affects the output characteristics of the PLL.This section is based on the maximum tuning voltage of HMC833 in the VCO chip of 5V, so the passive two order loop filter is adopted.The time constant can be obtained by the phase margin equation and its partial differential equation [5].The phase margin expression is shown below.
) 2 arctan( ) 2 arctan( 180 The partial differential of the angular margin diagonal frequency: The value of Ct can be approximated by the loop gain of 1, so there are the following formulas.The calculation of the capacitance resistance parameter can be obtained by the above method.According to the above formula, in the calculation, we need to know the gain of PLL detector, the gain and the frequency division ratio of VCO, and the expected performance parameters such as phase margin and loop bandwidth.Then the corresponding circuit element value can be estimated.If the phase margin of the phase locked loop is generally between 40 and 60 degrees, the system has better stability.The loop bandwidth is taken between one percent and 1/10 of the reference frequency, and the EITCE 2017 phase noise of the system can be better suppressed without losing the response speed.
The actual parameters of HMC833 VCO are shown in Table 1.

Reference frequency 5MHz
Charge pump current 2.54mA

Loop bandwidth 500kHz
Integer division ratio 53 According to table 1, the component values of the two order loop filter can be obtained, as shown in Table 2.

Simulink modeling and simulation
Using Matlab Simulink to build the model shown in Figure 5.In the Matlab simulation, the step signal is used instead of the input frequency signal fr, the frequency division ratio is 53, and the step signal initial frequency is 4000000kHz.As shown in Figure 6, the target output frequency is 5512028kHz.For ease of observation, the image is magnified at the time axis 20us.In Figure 6, ordinates represent frequency values, and abscissa indicates time.

Simulation results analysis
Figure 6 shows the two oscillations, the first oscillation that frequency from 0Hz jump to the starting frequency of 4000000kHz process.And the second oscillation that frequency from 4000MHz jump to the target output frequency 5512028kHz process.Figure shows that the system maximum overshoot is 5.82%, the system reach the steady-state value of 5512028kHz at 0.35us.
When the unit step signal is used as input, the responses obtained are shown in Table 3. From the above results, it can be analyzed that the maximum overshoot of the system is 20.96%, the regulation time is 0.845us, and the steady-state error is zero.This system has faster response speed, higher precision and meet the performance requirements of PLL frequency.Thus, it is proved that the design method of HMC833 loop filter is feasible.

Experimental verification
The experimental platform and the real-time output frequency display are shown in Figure 9.The HMC833 is controlled by FPGA with an output frequency of 551208Khz.The output frequency error curve that runs for 10 minutes is shown in Figure 10.The output frequency jump margin is 12Hz and the frequency lock accuracy is 1kHz.It has the characteristics of good stability and high steady-state precision.It satisfies the performance requirements of CPPLL for locking frequency, which verifies feasibility of the design method of HMC833 loop filter.

Figure 2 .
Figure 2. Schematic diagram of PLL The complete working flow of the charge phase-locked loop is that the input r f and the feedback voltage b f are controlled by PFD to generate the control voltage to control the opening and closing of the S1 and S2 in the CP, thus changing the charge pump current cp I .The cp I is filtered by LPF to produce a control voltage vco V , to control the output frequency of the VCO.The frequency signal generated by VCO is divided into PFD by NFD and compared with the input r f .So cycle until r f equals b f .

Figure 3 .
Figure 3. Simulink model Assume the gain of the PFD is

Figure 4 .
Figure 4. Passive loop filter model According to figure 4 shows that the main elements of the second-order loop filter are C1, C2, R2.The ts transfer function is shown in the following formula.

1 Tand the 2 T
=C1C2R2/Ct, 2 T =C2R2,Ct=C1+C2.The 1T are loop time constant.The Ct is the total capacitance of the loop.

K
is phase detector gain.The cp I is charge pump output current.The relation between d K and cp I is shown in the following formula.

Figure 6 .
Figure 6.Time domain response For accurate index analysis, the input signal is set to the unit step signal in Matlab simulation.The time domain step response curve and the open-loop response in the frequency domain are shown in Figure 7, Figure 8.

Table 2 .
Component value