X-band Core Chip SiGe design for Phased Array T/R Modules

The structure of the Core Chip for Phased Array T R Modules is presented. Methods for the formation of a phase delay for X phase shifters are considered. An original differential design of SiGe core chip for X-band is presented. The schematic of 5 bits phase shifter and attenuator are designed. It consist of a series number LPF and HPF filters. Gain of phase shifter is 1.5 dB. Attenuator has the adjustment range from 0 to 24dB. Linear output power of the core chip is 5dBm. The total consumed current of the device is 158mA, at 5V power supply.


Introduction
Improving the efficiency of microwave radio and radar equipment is associated with integration increasing , mass-dimensional characteristics improving, reliability increasing due to the reduction of wire bonding between the chips, repeatability of parameters improving; unification of the transceiver equipment increasing, radiation resistance increasing due to the use of widebandgap semiconductors of the A 3 B 5 group, increasing resistance to electromagnetic radiation by reducing the length of the connections.Regarding of that, the transceiver module parameters improving, of which core-chip is an integral part, is an important task.
The block diagram of the core-chip is shown in Fig. 1.It contains three ports switch (sw rt ), an attenuator, a phase shifter (Ɏ), signal amplifiers (A), a low-noise amplifier (LNA), a power preamplifier (PPA) and a switching device (PSSw), based on parallel or series to parallel interface.Phase shifters are a set of, usually, sequentially connected elementary cells.Elementary phase-shift cells can be performed on the in the next configurations: delay lines (for example microstrip lines, figure2a), combinations of HPF and LPF filters (figure2b), differently loaded transmission lines (figure2c), use of vector summing of mutually orthogonal I and Q signals (Figure 2d), which can vary in amplitude.

Fig. 2. Methods for forming phase delay
As a disadvantage of sequential connected elementary phase shifters is the influence of the impedance of the previous stage on the subsequent stage, which leads to a weakening of the transmitted signal, as well as to an additional phase shift.
Schematics of attenuators are also a series connection of elementary attenuators.It is most appropriate to use resistive dividers as signal attenuators.
At present, there are a large number of industrially mastered solid-state core-chips containing phase shifters and attenuators manufactured by such companies as OMMIC [1], MACCOM [10] (USA), UMS (France) [2], SELEX Sistemi Integrati SpA (Italy) [4], METDA (China) [8] based on A 3 B 5 semiconductor (Table 1).There are a number of works in which silicon technology based on nanoscale CMOS [6,10] or HBT [4,5] are used (Table 2).It should be noted the merits of using silicon technology based on SiGe bipolar transistors, which have a high upper limiting frequency [11] up to 300 GHz.This allows you to receive devices operating in the X and Ku bands

SIGE CORE CHIP DESIGN
The aim is to investigate the possibilities for designing a control chip (core chip) for X-frequency band using SiGe BiCMOS technology.
The chip should include the following blocks: attenuator, phase shifter, receive/transmit switches, compensating amplifiers, control circuit with parallel interface with TTL levels.Given the high high cutoff frequency of heterojunction bipolar transistors (HBT), it is advisable to design the crystal by using of SiGe BiCMOS technology [11].Differential current switches with a stabilized reference voltage were selected for base schematic high-frequency data signal processing units.
With this approach, the implementation of switches and amplifiers with the required parameters at frequencies up to 11 GHz has not technical difficulties, with the exception of output drivers, which have fundamental limitations in signal amplitude.The most critical are two blocks: a phase shifter and an attenuator.To demonstrate the capabilities of the technology, a four-phase phase shifter with HBT as active components was analyzed.The proposed schematic of the device is shown in Figure 3.

Parameters
Ommic [1] GaAs UMS [2] GaAs The inputs of the second switch are connected to the outputs of the two channels of the first switch, and its outputs are loaded on pairs of filters HPF22 and LPF22b.Similarly, the inputs of the third key are connected to the outputs of the two channels of the second switch, and its outputs are loaded onto the HPF45 and LPF45 filter pairs.
The fourth amplification switch (selector2to1_14m3), consumes 14.3 mA of current and performs the function of an analog multiplexer 2:1 with an activated or disabled inversion of the output signal.
The developed phase shifter was simulated using the Cadence system under various operating conditions in the frequency range from 9.1 GHz to 10.3 GHz.Absolute and relative phase shifts in the first three stages of the phase shifter at a frequency of 10 GHz and at two limiting temperatures of 0 ° C and + 125 °C are given in Table 5.
Table 3 The presented data demonstrate the acceptable stability of all stages.Additional phase adjustments can be made using a varcrl test voltage, which provides an additional adjustment range of about 8 °.The relative phase shift in steps at 125 ° C (worst case) in the frequency range from 10.0 GHz to 10.3 GHz is shown in Figure 4a.The accuracy of the phase setting is not worse than ± 0.7 °.The relative phase shift in steps at 125 ° C (worst case) in the frequency range from 8.0 GHz to 12 GHz is shown in Figure 4b.The phase shifter is the most significant block in the area of the core chip.The main area in the layout of the phase shifter is occupied by inductors, capacitors and varactors.The area of the block is 1,0ɯ1,0 mm 2 .
The main task of designing a controlled attenuator is to maintain the linearity of the input buffer at substantially different amplitudes of the input signal.For this, it is necessary to attenuate the signal before feeding it to the first amplification stage.This problem is solved by using a resistive ladder R-2R.The diagram of such ladder is shown in Figure 5.It is easy to calculate that the equivalent resistance of the ladder at node d1 is 50 Ohm.At the same time, the signal at the node d2 is divided by 2 times, at the node d3 -4 times and at the node d4 -8 times.Combining signals from all four nodes, you can get a total signal with a transmission factor from + 5.5dB to -18dB, which corresponds to the adjustment range from 0 to 24dB.Fig. 5 The schematic of the resistive ladder R-2R It should be noted that such system provides a binary adjustment of the attenuation, which allows simplify circuit implementation with a lower power consumption.The logarithmic adjustment system requires a much more complex circuit that contains a decoder and one or two switches per attenuator state, which contains up to 30 switches for a 4-bits.In this regard, was implemented a scheme 4-bit binary controlled attenuator.The shematic is shown in Figure 6.The developed attenuator was simulated by using the Cadence system under various operating conditions in the frequency range from 0 to 12 GHz.The attenuation drop by 3 dB occurs at a frequency of 11.8 GHz with a current consumption of about 35 mA.
The adjustment modes were checked by sequentially switching the binary signals sel1, sel2, sel3 and sel4 as shown in Figure 9.The linearity of the attenuator was determined from the attenuation of the second and third harmonics with respect to the magnitude of the signal at the fundamental frequency with three values of the amplitude of the input signal.The attenuation of second harmonic is -50 dBc and third harmonic is -45 dBc.

Conclusions
The estimated design of the core chip, by using of SiGe technological process, satisfying the different requirements for transmitting and radar equipments.
Phase shifter provides a phase shift from 0-360 degrees, phase discrete is not worse than 11 degrees, which corresponds to 5 bits of control(at the 9.1 to 10.3 GHz).A phase shifter without a fourth stage and an output amplifier provides a gain of 1.5dB (at 125 °C).In this case, four stages of the phase shifter consume a current of about 58mA, and the complete circuit is about 123mA.
The output stage of the phase shifter provides a differential linear power of about -1dBm.It is possible to increase the output power by about 2 times (up to + 5 dBm) due to the increase in the current consumption; The bandwidth of the attenuator (-3 dB) is 11.8 GHz in the worst case (at 125 °C) with a current consumption of about 35 mA.The attenuator gain is from + 5.5dB to -18dB, which corresponds to the adjustment range from 0 to 24dB.The total consumed current of the device is 158mA, (at 5V power supply) does not exceed 1W.
The using of different technologies bases (GaAs, GaN, SiGe), allow the implement of a transceiver module with optimal characteristics for any radar system.

Fig. 1 .
Fig. 1.Core chip block diagram Three-port switches (SPDT) for receiving/transmitting can be realized as solid-state electronic or micromechanical switches, made by using of integrated technology.

Fig. 4 .
Fig. 4. The relative phase shift in steps a)-range 8-12GHz, b)-range 10-10.3GHz The output stage in this circuit provides a linear power of 1 dBm.In this case, four stages of the phase shifter consume a current of about 58 mA, and full circuit is about 123 mA.It is possible to increase the output power by a factor of 2 (to +4 dBm) by increasing the current consumption.The phase shifter is the most significant block in the area of the core chip.The main area in the layout of the phase shifter is occupied by inductors, capacitors and varactors.The area of the block is 1,0ɯ1,0 mm 2 .

Fig. 9 .
Fig. 9.Control bits at the attenuator inputThe resulting differential output signal for the case of a constant amplitude of the input signal at a frequency of 10 GHz is shown in Figure10.

Table 1 .
Core chip parameters based on GaAs

Table 2 .
Core chip parameters based on Si 3.3;-3.3Chip Size (mm 2 ) 6.9 x 1.6 3.8 x 4.1 3.5 x 2.4 4.6x2.6 SPDT switch is a two-stage linear amplifier with a current consumption of 15.4 mA, the second stage of which performs the function of an analog demultiplexer 1:2.One of the outputs of the multiplexer is activated by the digital signal sel2, which ON/OFF the reference voltages by CMOS switch (sw2rfb25m_2v5).The principal feature of this circuit is the possibility of smooth phase adjustment within 2 ° by changing the analog voltage (varcrl) on varactors.Two pairs of phase-shift filters are connected to the outputs of the first amplifying switch.In this schematic, the HPF0 cells are equivalent transmission line, and the LPF22a cells are LC low-pass filters.
. Phase shift in amplification switches