Low Power CMOS Operational Amplifier with Integrated Common-Mode Feedback for Data Converter

The development a high-performance design of analog circuits becomes increasingly challenging with the continuous trend towards reducing the voltage supply and low power consumption without neglecting the trade-off among other performance parameters. This paper presents the design and implementation of CMOS operational amplifier (op-amp) with integrated common-mode feedback (CMFB) circuit for data converter using 0.13-μm Silterra CMOS technology. The folded cascode topology is employed as a main op-amp design because it provides high gain and high bandwidth besides low power consumption. The simulation results indicate that the DC gain of 64.5 dB along 133.1 MHz unity gain bandwidth (UGB) is achieved for a 1 pF load capacitor. The slew rate of 22.6 V/μs, the phase margin (PM) of 68.4 ° with settling time of 72.4 ns are obtained. The power consumption of this op-amp is 0.3 mW through voltage supply of 1.8 V.


Introduction
Wireless Operational amplifier is a core element and integral part for most analog and mixed-signal systems.The behavioral of op-amp such as high gain, high input impedances, low output impedance, high bandwidth and fast settling makes this device often used amongst multiplicity of applications like in pipeline ADC.Traditionally, op-amp can be classified into several topologies which are telescopic, folded cascode, two-stage and gainboosted [1].Each topology has their own compensation, but they can be applied in any design op-amp circuit by considering the performance parameter.
A telescopic op-amp is a simple topology and provided a high gain as well faster performance [2,3].This topology is called as 'telescopic' because the cascades are attached between the voltage supplies with the transistor in the differential pair, occurs in a structure where each branch of the transistor connected directly together in a straight line [4].Commonly the telescopic topology has a slighter swing because of lesser current legs and produces a small power consumption and low noise.
In a folded cascode op-amp, the topology is normally customized from the telescopic op-amp and it issues higher gain and performance [5,6] compared to the telescopic because it consumes more currents legs.This topology is called 'folded cascode' because of small signal current is folded up or to down [1].Generally, this op-amp allows the particular input common-mode level of being near to the voltage supplies as well as performing a high output swing, wide input common-mode range and preferably steering in low voltage supply circuits [4].However, this topology contributed greater noise that effect from the more currents legs.

Design constraints
A design constraint is a key element in preparing the best performance of op-amp circuit.As a requirement of a high speed and high accuracy in pipeline ADC, there are numerous constraint parameters that should be considered such as gain, unity gain bandwidth, phase margin, slew rate and also output swing.Each parameter constraints are explained as follows.

Gain
Ideally, the gain is the product of the transconductance structure over the output resistances of the load structure that express as: where the gain extremely depends on the frequency of the input signal of an amplifier.

Unity gain bandwidth
The unity gain bandwidth state that the frequency at which the open loop gain of the amplifier is unity with the maximum capacitance at the output node.Thus the UBW is obtained as:

Phase margin
The purpose of phase margin (PM) is to determine the stability of the amplifier where the higher values of PM will allow the output signal to achieve a stable state without much swing.Noted that the PM is depends on the applications [1].

Slew rate
Slew rate is defined as the rate of change in the output voltage that caused by a step change on the input.It can be determines by the output capacitance and the current across the output branch.
Slew rate = I out / C L (4)

Output swing
This constraint relates to the output of the op-amp where the saturation voltage of load structure mainly defines the output swing of the op-amp.Commonly, most systems employing op amps require large voltage swings to accommodate a wide range of signal amplitude [1].

Design implementation
According to the op-amp specifications as presented in Table 1, the desired op-amp topology was determined.Folded cascode topology idyllically to be principle op-amp for this work since the design has been used in [7] for obtaining fast settling, high gain and high unity gain bandwidth besides low power consumption.The architecture of folded cascode op-amp with common-mode feedback is illustrated as Fig. 1.Traditionally, the folded cascode op-amp has been designed by using a pair of PMOS type or NMOS type for the input range of op-amp through the limits of input common mode range [7].For this work, the NMOS type is chosen to be an input of the differential amplifier since this input type can assign more large output gain compare to PMOS input type.As shown in Fig. 1, the folded cascode topology consists of two different structures which are NMOS differential amplifier (M1-M3) and folded cascode structure (M4-M11).The open loop voltage gain can be determined as: where g m is a short-circuit transconductances of the output current gain across the transistor of M6 and R o is the output impedance of folded cascode by looking into the drains of M6 and M8.R o = g m6 .ro6 (r o1 ||r o4 ) || (g m8 .ro8 .ro10 ) (7) Therefore, the gain is expressed as: Meanwhile, the gain bandwidth of the folded cascode circuit is: where g m1 is a transconductance of M1 and C L is the capacitance at the output node.
A CMFB circuit (M12-M16) is designed in order to fix the voltages at high impedances node to the desired voltage value of CMRR performance while ensuring the stability of common-mode voltage for fully differential op-amp [8].As referred in Fig. 2, M12 is assigned to be a feedback to the folded cascode op-amp while M13 and M14 is an input of CMFB that attaches to the output of folded cascode op-amp and M15 represents as a reference voltage.This CMFB architecture is modified from the conventional amplifier as in Fig. 1(a) in [9].The modification is based on M12 because its need a stable voltage to fed the folded cascode op-amp.Subsequently, these two circuit blocks are implemented in 1.5-bit per stage pipeline ADC as shown in Fig. 2 in order to simulate the circuit performances.The result is discussed in section below.

Results and discussion
The proposed folded cascode op-amp was designed using Cadence Software and implemented in 0.13-μm process technology with 1.8 V supply voltage whereas the simulation of circuit via Cadence Virtuoso spectre.The circuit design is analyzed in two methods which are AC analysis and Transient analysis.Table 1 Fig. 5 illustrates the result for implementation of the circuit in 1.5 bit per-stage pipeline ADC.The performances of the circuit are referring to the process information as tabulated in Table 2.The comparison for folded cascode op-amp performances between previous works is summarized as in Table 3. From the table, this circuit design attains low power consumption with smallest load capacitance; therefore the chip size can be reduced.

Conclusion
The design and implementation of CMOS op-amp with integrated common-mode feedback circuit for data converter using 0.13-μm Silterra technology is presented.The DC gain of the op-amp is obtained about 64.5 dB along with unity gain bandwidth (UGB) of 133.1 MHz for a 1 pF load and 68.4 degrees.The circuit in this work consumes a low power consumption which is around 0.3 mW at 1.8 V supply supply.The simulation result shows that the proposed design is suitable for data converter applications.
Fig. 3 shows the AC analysis result of the proposed circuit.The simulated DC gain demonstrated 64.5 dB with 68.4 degrees of phase margin (PM) as shown in Fig. 3 (a) and Fig. 3 (b), respectively.Meanwhile, the transient analysis result is depicted in Fig. 4. The slew rate performs 22.6 V/μs among 72.4 ns of settling times.

Table 1 .
Op-amp Specifications for Pipeline ADC.

Table 2 .
Data converter information for 1.5-bit per stage pipeline ADC.

Table 3 .
Folded cascode op-amp performances.This work was financially supported by the Fundamental Research Grant Scheme (9003-00387).