Process Parameters Optimization of 14 nm MOSFET Using 2-D Analytical Modelling

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.


Introduction
The gate length of MOSFET has continually been scaled down through last few decades to create smaller and smaller device in order to fabricate high density chips.Reduced power dissipation, faster switching and low cost were the main concern for this scaling.As MOSFET is scaled down it provides various kind of technical challenges and this become worsen when it comes to the nano-meter dimensions.This is because of the problems such as Short Channel Effects (SCE), increased leakage current, and lack of pinch off [1].The utilization of SiO 2 to overcome the problems is no more effective today.Researchers has come up with a new solution to overcome the scaling impact by replacing the gate dielectric from SiO 2 to high permittivity materials and innovations to new device structure such as Finfet and double-gate.In this research, the virtual fabrication was simulated through ATHENA module and its electrical characteristic was simulated via ATLAS module where both modules can be found in Silvaco TCAD Tools.These modules are important in designing and optimizing the process parameter [2] of a semiconductor device.As part of optimization process, Taguchi Method were used to observe the variance and mean effect of process parameter.With added noise factor called signal-to-noise ratio (SNR), this method becomes more reliable.The aim of this research is to virtually design and optimize a 14nm high-k metal gate CMOS transistor with threshold voltage, V TH of 0.2301V and leakage current, I OFF lower than 100nA/um.The values are set by ITRS 2013 specification.

Virtual transistor simulation recipes.
For simplicity, the transistors were designed separately in ATHENA module.The summarized simulation recipes were shown in Table 1.The complete virtual design of 14nm NMOS transistor is as shown in Fig. 1.The same structure was used to design the PMOS transistor except the utilization of metal gate which is Titanium Silicide (TiSi 2 ).   2 shows the value of each parameter at different level and Table 3 shows their noise factors for both type of device.

Results and analysis
Taguchi method was applied in this research to optimize the threshold voltage (V TH ) and leakage current (I OFF ).By following the L9 Orthogonal Array template, all four control factors are varied accordingly using the dopant values for which produced the output near to the ITRS 2013 prediction.In this experiment V TH belongs to nominal-the-best quality characteristic while I OFF belongs to lower-the-best quality characteristic.The initial results of V TH and I OFF after optimization are described in Table 4 and Table 5 for NMOS transistor and PMOS transistor respectively.The next step is to determine the dominant and the adjustment factor for both transistors.The results were summarized in Table 6 for both V TH and I OFF .For NMOS device, it can be seen that Halo Implantation (A) shows the highest influence on V TH (40%) and hence it was set to be the dominant factor.Halo tilting angle (B) on the other hand displays the lowest impact of 13% on variance but score the highest on Mean (29%).Thus, parameter B was set to be the adjustment factor.Parameter B was then varied between 31° to 33° to get the V TH value near to ITRS 2013 prediction.For I OFF , S/D Implantation (C) gives the highest impact (79%) to the device and thus it was set as a dominant factor.
The S/N response for PMOS device shows parameter A as the dominant factor because of the highest influence on V TH (52%) and parameter B as the adjustment factor due to highest score on mean (56.23%) and lowest score on variance (32%).Parameter C and D was neglected and considered null as the percentage scores below 10%.It is because any changes made to parameter C and D will not influences the device performance.Parameter B was swept between 19.7° to 19.9° to get the V TH within the ITRS 2013 prediction.The same response for I OFF as parameter A possess the highest value on Mean (46%) and thus was set to be the dominant factor.

Conclusion
The modeling and optimization of 14nm gate length high-k metal gate CMOS transistor was successfully presented.The optimization of threshold voltage (V TH ) and leakage current (I OFF ) through Taguchi analysis was also fully utilized together with Silvaco TCAD Tools for virtual design simulations.The results were reported to be well within ITRS 2013 prediction.
We would like to thank Universiti Tenaga Nasional (UNITEN) and the Malaysian Ministry of Education for sponsoring the publication of this work using grant 20140123FRGS.

2. 2
Taguchi L9 orthogonal array method.The optimization of the transistors was done using Taguchi Method by variation of the process parameters.The parameters that has been selected in this research includes Halo Implantation Dose (A), Halo Tilting Angle (B), Source Drain Implantation (C), and Compensation Implantation (D).Noise factors on the other hands includes Sacrificial Oxide Layer Temperature, BPSG Temperature and V T Adjust Implant Temperature.Table

Table 2 .
Control Factors and Their Levels , 8

Table 3 .
Noise Factors and Their Levels

Table 4 .
V TH and I OFF Results for NMOS

Table 5 .
V TH and I OFF Results for PMOS , 8

Table 6 .
S/N Response and AnnovaThe best setting parameters for both devices based on the Taguchi analysis are shown in Table7.The best setting of parameter values was simulated again at different noise factor to verify the accuracy of Taguchi analysis.The result of the confirmation experiment based on different noise factors are shown in Table8.Final results were then compared to ITRS 2013 prediction for conclusion of the optimization process experiment which is shown in Table9.

Table 7 .
S/N Response and Annova

Table 8 .
Results of Confirmation Experiment