Operations on Multiple Transition Faults without Enumeration

The multiple transition fault model has been used to represent alternative defective gate combinations in the circuit. However, the number of faults is very large even of modest size circuits and therefore the defective configuration may not be considered. It is shown that multiple transition faults can be stored compactly in Binary Decision Diagrams. Furthermore, important operations for identifying the location of failures are implemented without fault enumeration. Experimental results on some of the largest ISCAS’85, ISCAS’89. and ITC’99 benchmarks demonstrate the scalability of the proposed method.


Introduction
With the technology moving to nanometer regime, the task of testing and diagnosing failures in integrated circuits (ICs) has become very demanding. Reductions on the area of the chip combined with increase in the number of transistors can cause delay defects.
The process of identifying the location of failures in an IC is guided by a set of possible fault sites [1]. This process is guided by a set of possible fault sites in the IC called suspects. Methods like [2]- [3] are restricted to a single defect location. This is very unlikely to be the case in deep submicron.
The path delay fault model is used to delay defects in deep submicron since it allows for many small delay defects to be distributed along a failing path [4]- [5]. Although effective in testing, its use in identifying the defective locations is limited [6]- [8]. The transition fault model [9] is used, but the authors assume that only one fault is being generated at each node. This is rarely the case in deep submicron. This may turn out to be a restriction that may misguide the identification of the location of failures.
This paper uses the multiple transition fault model (MTF) along sensitized paths to represent alternative defective gate combinations in the circuit. The number of MTFs is much higher than the number of PDFs. Transition fault based approaches in [10]- [11] do not scale well to the complexity of this model.
Fault implicit algorithms on appropriate data structure are used in this paper, to cope with the such scalability challenges. In this paper, we use the term test vector to denote a pair of input test patterns. The main contributions of this paper are: 1. Algorithms to compute and store in a non-fault enumeratively manner the number of MTFs that are excited by a bad vector (the initial suspect set) as well as by a set of good vectors (the good set). 2. Algorithms to prune the suspect set using the good set and guide the identification of defective locations. 3. A thorough experimental evaluation to demonstrate the impact of the proposed method.
This paper is organized as follows. Section 2 gives an overview of the proposed method. Section 3 describes the proposed method. Section 4 gives experimental results and finally Section 5 concludes.

Overview of the proposed method
We define the hit rate as the frequency of a gate in the MTFs that are sensitized by a bad vector (also called the bad set). The proposed tool will produce the hit rate of all gates. Gates with higher hit rates are most likely to have a defect and the silicon debugger should first examine those gates. Consider the circuit in Figure 1. For simplicity in the exposition, we assume that all nodes have unit delay. Furthermore, we assume that the total delay defect observed (along any path) is at most one unit. Therefore, we assume that defective nodes reside along paths with the longest number of nodes.
In this example there are no inverting nodes, and therefore, all transition faults are rising. For brevity, in the following we do not explicitly indicate that the faults are rising. In Figure 1, the bad vector T1 = {10100,11101} sensitizes rising transitions along paths P1 = {1-5-7-10-12} and P2 = {4-6-9-11-12}. MTFs occur along these paths and a delay of unit 1 is observed at gate 12. A possible MTF is {1,5}, where each number indicates the gate id. This MTF may occur because both gates belong to the same path and the sum of potential defects associated to these gates may sum up to 1 unit. Another MTF is {1,4,5,7,9,10}. In this MTF possible delays on nodes 4 and 9 (which are on the same path) may sum up to 1 unit and possible delays on nodes {1,5,7,10} (which are on another path) may also sum up to 1 unit of defect.
In this example, MTF {1,4} may occur if one unit of defect is lumped on gate 1 and also one unit of defect is on gate 4. (Two gates are in different paths). The total number of MTF in this example is 511. In general, the total number of MTFs grows super-exponentially to the number of gates on the sensitized PDFs. It is a huge number even for a small number of paths. This paper presents algorithms that utilize the data structure in [12]. It is shown that is capable of storing very compactly a huge number of MTFs.
In Figure 1, the rising transitions faults at gates 1,4,5,6,7,9,10,11 and 12 have 256 hit rate in the total MTF initial suspect set MTFinitial. Therefore, there is no indication on which gate should be examined first for defects. The process may be assisted by good vectors. We will show a methodology on how to remove MTF from a suspect set and change the hit rate of fault sites in MTFinitial.

Generation, storage and manipulation of faults without enumeration
The advantage of the deductive method [16] is that all sensitized MTF by a single test vector, can be generated with a single topological traversal of the circuit netlist. Figure 3 shows an example of MTF generation using the deductive method. Let a test vector be T = {01, 11}. At each gate, all possible MTF that may occur until that gate are stored in ZBDD data structure [12]- [14].
Our method constructs two main MTF sets. One set is generated for the good set and one for the bad set. For the bad set we generate MTF along robust and non-robust PDFs. For the good set only long robust and validatable non-robust PDFs are considered [5]. The generation rules at each gate are the same for bad and good sets. A gate it is marked if it belongs to an appropriate PDF. The MTF generation takes into consideration only marked gates.
MTFs are generated non-enumeratively using basic operations in ZBDDs. Table 1 shows some basic ZBDDs operations being used in our approach. (More details about ZBDDs operators can be found in [12] and [13].) We represent the MTFs as combinational sets in the ZBDD. In Figure 4 we give an example of the representation of the MTFs on the sensitized circuit path of Figure 4(a) to its ZBDD shown in Figure 4(b). The ZBDD is a directed acyclic graph. Node 0 in Figure 4

Union (A, B)
A U B The union operation

Prod (A, B)
A ∩ B The unate product operation

Subset (A, B)
A C B The subset operation

Diff (A, B) A -B The set difference operation
The generation of the MTF obeys the rules showed in Table 2 for the case of an AND gate. (We generate tables for all gates in the same manner.) At each simulation test vector T, we traverse the circuit in a topological manner. For each gate, rules from Table 2 are used to generate an MTF. Let us assume a 2-input AND gate whose inputs are labeled a, b and its outputs labeled c. When addressing the gate MTF that have propagated until inputs a and b are stored explicitly in a ZBDD. The table shows how to generate the MTFs at output c. They are generated in a non-fault enumerative manner using the operators in Table 1, and are kept as list MTFC in the ZBDD. We illustrate the method circuit shown in Figure 5. Let test set T consists of three test vectors T = {T1, T2, T3}. Assume that vector T1 = {1010, 1000} is a bad vector and PDF P1 = {2-6-8-9-10} is sensitized as shown in Figure 5 PDF P1 is sensitized robustly [15]- [16], and therefore has no defect. Gates 3,8,9,10 Test vector T3 sensitizes a non-robust PDF P3 [15], [16]. We cannot guarantee that this PDF has no defect. However, P2 and P3 together they form a VNR test [5] and therefore, it is guaranteed that P3 has no defect. Gates 1,3,5,8,9,10 MTFfinal = {{2}, {2,8}, {9}, {2,9}, {2,8,9}, {2,10},  {2,8,10}, {2,9,10}, {2,8,9,10}, {6}, {{2,6}, {6,8},  {2,6 For a single vector our method runs one traversal to generate all the possible MTFs. Moreover, simple ZBDD operations and algorithms, that are not described in this paper, can produce the transition fault sites with the highest ranking rate. The frequency of appearance of a gate inside the set MTFfinal determines the order of inspecting during silicon debug.
The frequency of all gates can be identified by traversals on MTFfinal [17]. The gate with the highest hit rate that is used for silicon debug.

Experimental results
We experimented on a Unix machine with 8 GB memory and 2.40 GHz. The algorithms were implemented in C++. The ISCAS '85, ISCAS '89 and ITC '99 benchmarks were used as the circuits under test. In our experimentation, we had 3 bad vectors and 40,000 good vectors, for each benchmark. All gates were assumed to have unit delay. It was asserted that the total delay defect did not exceed two units of delay, and, therefore, MTFs generated only along the longest and second longest paths in each benchmark. Table 3 reports our experimental results. Column 2 shows the size of MTFinitial, i.e., the number of MTF sensitized by bad vectors. Column 3 reports the total number of good MTF, i.e., the size of MTFgood consisting of MTFs from robustly and validatable non-robustly sensitized PDFs by the 40.000 good test vectors.
Column 4 shows the reduction in the suspect set using set MTFgood. In benchmarks such as s38584 and s9234 the number of total MTFs was huge and we could not enumerate them. Therefore, data structures such as arrays could not be used to store them efficiently. However, our method uses the ZBDD data structure and stored all the MTFs. The results for benchmarks s38584 and s9234 show the effectiveness of ZBDD data structure. Column 5 shows the percentage reduction in the suspect set MTFinitial. Observe that the average reduction of the suspect set is 83.41%. In circuit c6288, the reduction is only 0,5% but the number of eliminated suspect MTFs is 1.030e+16, which is a huge number.
Columns 6 and 7 show the impact of the proposed approach in silicon debug. The numbers in the cells are the gate labels and the characters in parenthesis are the type of the transition ({r} for rising and {f} for failing). Column 6 reports for each benchmark the top two transition fault sites in order that appear more often in the set MTFinitial. Column 7 shows the same information for MTFfinal. In bold fonts we list all gates that do not appear in column 6. The results show the impact of pruning for silicon debug.  . Column 6 reports for each benchmark the top two transition fault sites in order that appear more often in the set MTFinitial. Column 7 shows the same information for MTFfinal. In bold fonts we list all gates that do not appear in column 6. The results show the impact of pruning for silicon debug.
Column 8 lists the total CPU time (in seconds) by the proposed method. Columns 2, 3 and 4 show the total number of MTFs generated. It is clearly shown that the approach is fault implicit.

Conclusion
A method to guide silicon debug for delay defects has been proposed in order to guide silicon debug for delay defects. The collection of suspect MTFs has been generated implicitly by considering appropriately sensitized path delay faults for the bad and the good vectors. A method to effectively prune the initial suspect collection of MTF faults has been proposed and its impact has been evaluated experimentally.