Rapid prototyping of Networks-on-Chip on multi-FPGA platforms
1 College of IoT, Hohai University, 21300 Changzhou, CHINA
2 Hubert Curien Laboratory UMR CNRS 5516, 42000 Saint-Etienne, France
3 TIMA Laboratory, UJF/CNRS/Grenoble INP, 38000 Grenoble, FRANCE
Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms.
© Owned by the authors, published by EDP Sciences, 2016
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.